Input/output interface for data in parallel processors

Details Input/output interface for data in parallel processors Input/output interface for data in parallel processors

1992-02-19

1994-09-06

Richardson, Robert L.

G06F 1300

Patent

active

053455630

ABSTRACT:
An input/output interface for converting between data patterns in bit-parallel and word-serial format and data patterns in word-parallel and bit-serial format. In combination with a parallel processor, the inputting and outputting rates of the data are to be increased. To this end, a three dimensionally organized memory with a three-dimensional addressing is connected to the input and/or to the output of the parallel processor. Each address is composed of three components, of which a first component represents the significance of a bit, the second component represents the running number of the word in a limited sequence of words, and the third component represents the running number of the sequence, to which the word belongs. A switching network for the control of the memory is associated with the memory. The memory is arranged to buffer an incoming data stream of bit-parallel and word-serial format. The data from the memory are applied to the parallel processor as bit-serial and word-parallel data pattern in the form of "bit planes" of identical bit addresses. Alternatively, the memory may serve to buffer a data stream provided by the parallel processor in bit-serial and word-parallel format as a sequence of "bit planes" , the data being outputted as a bit-parallel and word-serial data pattern.

REFERENCES:
patent: 3911409 (1975-10-01), Kowal
patent: 4254473 (1981-03-01), Galdun et al.
patent: 4514807 (1985-04-01), Nogi
Kittler and Duff "Image Processing System Architectures", Research Studies Press Ltd., Letchworth, Herts, 1985 pp. 23-35.

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