Input/output electrostatic discharge protection circuit for an i

Details Input/output electrostatic discharge protection circuit for an i Input/output electrostatic discharge protection circuit for an i

1996-12-19

1999-10-05

Sherry, Michael J.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 257355, H02H 322

Patent

active

059634090

ABSTRACT:
An input/output electrostatic discharge (ESD) protection circuit for an integrated circuit disposed between an input/output port and the internal circuitry, including an input path protection device and an output path protection device. The output path protection device includes a pair of pull-up and pull-down transistors, two resistors, and a first and a second MOS field effect transistors respectively connected in parallel with the pull-up and the pull-down transistors. The resistors are formed in lightly-doped regions of the source or drain of the pull-up and pull down transistors, respectively, so the series resistance can be reduced efficiently, the driving ability can be prevented from decreasing and the devices can obtain uniform breakdown under intensive layout circumstances. The first and the second MOS field effect transistors are utilized to protect against both positive electrostatic stress and negative electrostatic stress to improve overall ESD protection.

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