Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2002-05-30
2003-07-29
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
Reexamination Certificate
active
06600348
ABSTRACT:
BACKGROUND OF THE INVENTION
FIG. 1
illustrates in block diagram form a microprocessor
10
coupled to memory device
12
via a data bus
14
. Although not shown, data bus
14
includes a plurality of conductive lines, each one of which is capable of transmitting a data bit signal between memory device
12
and microprocessor
10
.
Microprocessor
10
includes a plurality of input/output (IO) devices (not shown in
FIG. 1
) coupled to respective conductive lines of data bus
14
. IO devices transmit or receive data bit signals.
FIG. 2
is a schematic diagram of a driver
16
contained in one of the IO devices of microprocessor
10
. Driver
16
drives one of the conductive lines of data bus
14
in response to receiving an input data bit signal.
Driver
16
includes a p-channel field effect transistor
20
, an n-channel field effect transistor
22
, an input node
24
, and an output node
26
. Although not shown, output node
26
is coupled to a conductive line of data bus
14
. P-channel field effect transistors will be referred to as p-channel FETs, and n-channel field effect transistors will be referred to as n-channel FETs. N-channel and p-channel FETs include a gate, a drain, and a source designated g, d, and s, respectively. The gates of FETs
20
and
22
are coupled to input node
24
. The drains of FETs
20
and
22
are coupled to output node
26
. The source of FET
20
is coupled to V
dd
, while the source of FET
22
is coupled to V
cg
. V
dd
is a supply voltage provided from a source external to microprocessor
12
, while V
cg
is common ground.
In operation, input node
24
receives an input data bit signal D
in
directly or indirectly from the core of microprocessor
10
. Although not shown, D
in
is typically provided to input node
24
by a signal inverting circuit. The input data bit signal D
in
varies between two voltage levels V
dd
or V
cg
representing a binary one or a binary zero, respectively. In response to receiving D
in
, driver
16
chargers or discharges output node
26
and the conductive line of data bus
14
coupled thereto. When driver
16
receives D
in
equal to V
cg
, driver
16
charges output node
26
to V
dd
. When driver
16
receives D
in
equal to V
dd
, driver
16
discharges output node
26
to V
cg
. In this manner, driver
16
generates an output data bit signal D
out
at output node
26
that varies between V
dd
and V
cg
in response to receiving input data bit signal D
in
that varies between V
dd
and V
cg
.
P-channel or n-channel FETs are often referred to as electronic switches. A p-channel FET is active or “switched on” when its gate voltage V
g
is a threshold voltage V
t
or more below its source voltage V
s
. In other words, a p-channel FET is active when V
g
<V
s
−V
t
. When active, a p-channel FET provides a very low impedance path between its source and drain such that current can flow therebetween. When its gate voltage V
g
is greater than a threshold voltage V
t
below its source voltage V
s
the p-channel FET is inactive. In other words, a p-channel FET is inactive when V
g
>V
s
−V
t
. When inactive, essentially no current can flow between the p-channel FET's source and drain. In
FIG. 2
, p-channel FET
20
is active when the voltage of D
in
is V
cg
and inactive when D
in
is V
dd
.
An n-channel FET is active or “switched on” when its gate voltage V
g
is a threshold voltage V
t
or more above its source voltage V
s
. In other words, an n-channel FET is active when V
g
>V
s
+V
t
. When active, an n-channel FET provides a very low impedance path between its source and drain such that current can flow therebetween. An n-channel FET is inactive when V
g
<V
s
+V
t
. When inactive, essentially no current can flow between the n-channel FET's source and drain. In
FIG. 2
, n-channel FET
22
is active when the voltage of D
in
is V
dd
and inactive when D
in
is V
cg
.
N-channel or p-channel FET operation is subject to limitations. More particularly, the voltage V
gd
between the gate and the drain of the devices or the voltage V
gs
between the gate and source of the devices should not exceed a gate oxide voltage limit V
limit
. If V
gs
or V
gd
exceeds V
limit
in either a p-channel or n-channel FET, damage can occur to the FET that renders it permanently inoperable.
V
limit
(also known as gate oxide integrity) depends on failure in time (FIT) rate, the gate area of the FET, and/or the distance between the source and drain of the FET. The FIT rate requirement is provided by a system design specification. For p-channel and n-channel FETs manufactured using a 0.18 micron process, V
limit
may vary between 1.4-1.8 volts depending on how the p-channel FETs are operated. The V
limit
for p-channel and n-channel FETs of a particular size and used in a particular manner, can be determined based on experimental results.
The sizes of FETs, including the distance between sources and drains thereof, in microprocessors continue to reduce as semiconductor manufacturing technology advances. As FETs continue to reduce in size, so does their V
limit
.
As noted above, driver
16
operates to charge or discharge output node
26
, and thus the conductive line of data bus
14
and the memory device
12
coupled thereto, in accordance with the input data bit signal D
in
. Characteristics of driver
16
are subject to variations in operational parameters such as temperature and/or magnitude of supply voltage V
dd
. For example, an increase in operating temperature of driver
16
may increase its output impedance and potentially reduce driver
16
's drive strength or ability to fully charge or discharge output node
26
within a predetermined amount of time.
Notwithstanding variations in operational parameters, which are dynamic in nature, the actual output impedance of driver
16
may not match the expected impedance of driver
16
due to unexpected and permanent variations in the physical structure of FETs
20
and
22
. More particularly, microprocessors including their drivers are manufactured on silicon wafers using complex equipment and processes. Once completed, the microprocessors are severed from the silicon wafer and individually packaged for subsequent use. A single wafer, depending on its size, is capable of producing several microprocessors. In theory, each of these microprocessors should be identical to each other in physical structure. In practice, slight physical variations exist between these microprocessors. For example, due to variations in the fabrication process, the doping density in the source or drain regions of FETs
20
and
22
of driver
16
, or the length or width of gates of FETs
20
and
22
of driver
16
, may unexpectedly vary from microprocessor to microprocessor. These physical variations in the FETs are static in nature and may unexpectedly increase or decrease the output impedance of driver
16
.
Generally, the output impedance of driver
16
can be represented as its output voltage V divided by its output current I. As noted above, the output impedance of driver
16
may vary with, for example, temperature and/or magnitude of V
dd
.
FIG. 4
illustrates IV curves that plot the output voltage V of driver
16
versus the output current I of driver
16
. Each IV curve corresponds to driver
16
operating at different temperatures and/or magnitudes of V
dd
. The IV curves of
FIG. 4
were drawn with the presumption that no load is applied to output node
26
.
As can be seen from
FIG. 4
, each of the IV curves are non-linear which means that the output impedance of driver
16
varies with its output voltage. The IV curves of
FIG. 4
also show that output impedance of driver
16
varies with temperature and/or magnitude of V
dd
for a given output voltage V. The impedance of the conductive line and the memory device
12
coupled to output node
26
, however, is static or substantially static. As a consequence, a mismatch generally occurs between the output impedance of driver
16
and the combined impedance of the conductive line and memory device
Cappellano Ivana
Khieu Cong Q.
Romano Fabrizio
Yu Shifeng Jack
Campbell Stephenson Ascolese LLP
Cappellano Ivana
Nu Ton My-Trang
Sun Microsystems Inc.
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