Input/output command timing mechanism

Details Input/output command timing mechanism Input/output command timing mechanism

1978-10-23

1980-07-15

Miller, Charles D.

Boots, shoes, and leggings

G06F 300

Patent

active

042131782

ABSTRACT:
A monitor circuit for overseeing input/output activity in a digital computing system is disclosed. The circuit comprises a memory array for storing subchannel status words, each of which corresponds to an input/output operation unit. Each subchannel status word includes a timing monitor field having a current count subfield, a count limit subfield, and a command-in-progress bit position. Circuits are provided for incrementing at timed intervals numbers encoded in the current count subfields of those subchannel status words against which a request for an input/output operation is outstanding. A circuit is provided for comparing the numbers encoded in the current count subfields to the count limit subfields to determine if a response to a request for an input/output operation is overdue.

REFERENCES:
patent: 3828325 (1974-08-01), Stafford
patent: 3972023 (1976-07-01), Bodner
patent: 4016548 (1977-04-01), Law
patent: 4084228 (1978-04-01), Dufond
patent: 4103328 (1978-07-01), Dalmasso

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