Patent
1992-06-02
1994-11-08
Richardson, Robert L.
G06F 1300
Patent
active
053634888
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to an I/O command issuing control system in a data processing system, and more particularly to an I/O command issuing control system in a data processing system that allows efficient processing following issuance of an I/O command.
BACKGROUND ART
FIG. 1 is a block diagram illustrating a basic principle of a data processing system. Referring to FIG. 1, this data processing system comprises a processor module 30, adaptor modules (ADP) 42 and 42', and a system bus 41 connecting the processor module 40 to each of adaptor modules 42 and 42'. I/O devices (DV) 43 and 44, and 43' and 44', are respectively connected to the adaptor modules 42 and I/O devices 43, 44, 43' and 44' are auxiliary storages (such as disk drives). The processor module controls the I/O devices 43, 44, 43' and 44' via the system bus 41 and the adaptor modules 42 and 42'. Inside the processor module 40, a CPU 45, a memory module (MM) 46, and a bus controller 48 are interconnected via an internal bus (MPU bus) 47. The bus controller 48 generates a bus command used for transferring, to the adaptor module 42 (42'), via the system bus 41, an I/O command issued from the CPU 45. An I/O command on the basis of this bus command is transferred to the adaptor module 42 (42'). The bus controller 48 also notifies the CPU 45 whether or not the I/O command, transmitted from the adaptor module 42 (42') via the system bus 41, was successful in activating the I/O devices 43 and 44.
FIG. 2 is a flowchart illustrating a conventional I/O command issuing control process for a data processing system as that shown in FIG. 1.
Referring to FIG. 2, this I/O command issuing control process is divided into separate processes in a processor module 51, a system bus 52, and an adaptor module 53 (hereinafter simply called an adaptor). The processor module 51, the system bus 52 and the adaptor 53 are connected in the same manner as shown in FIG. 1 (although connections are not shown in FIG. 2).
A CPU in the processor module 51 issues an I/O command 54. This I/O command is transferred to a bus controller via an MPU bus. The bus controller modifies the I/O command so that the command is suitable for the system bus, and the modified I/O command is supplied to the adaptor (ADP) via the system bus 52. The adaptor (ADP) 53 that received the I/O command from the CPU notifies the bus controller of the processor module 51 whether or not control of an I/O device on the basis of the I/O command is possible, notification taking place by means of a response signal on the system bus 52. After receiving the response signal from the adaptor 53, the bus controller submits the response signal to the CPU.
After issuing the I/O command 54, the CPU of the processor module 51 waits for the response signal resulting from the I/O command 54 to be returned from the adaptor. When the CPU receives the response signal from the adaptor the CPU carries out an activation result determination 56. When it is determined in this activation result determination 56 that an I/O device has been activated, the CPU carries out a process 57 of issuing a next command. When it is determined that an I/O device has not been activated, a specified activation failure process 58 (including a reactivation process) is carried out.
In a conventional I/O command issuing control process like the above, after issuing an I/O command, the CPU in the processor module holds a process of issuing a next command and waits for a response signal to be reported from an adaptor. Due to a comparative largeness of scale of a system bus, and to other factors, it takes a relatively long time to transmit an I/O command from a processor module to an adaptor via the system bus, and to return a response signal to the processor module via the system bus. This waiting time has not been an obvious disadvantage as far as the CPU of low processing speed is concerned. However, with increased performance of CPUs in recent years and the increased processing speed of CPUs, the effect of the waiting ti
REFERENCES:
patent: 5220653 (1993-06-01), Miro
Hidaka Yuji
Kimura Makoto
Fujitsu Limited
Richardson Robert L.
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