Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-10-05
2001-12-04
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S534000
Reexamination Certificate
active
06326835
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integration circuit; and more particularly to an input/output circuit used therein.
BACKGROUND OF THE INVENTION
A conventional output circuit used in a semiconductor integrated circuit device, for example, includes a signal input terminal, an enable signal terminal, an inverter, a 2-input NAND circuit, a 2-input NOR circuit, a PMOS transistor, an NMOS transistor, a power supply terminal supplied with a 3 V power supply potential, a ground terminal supplied with a ground potential, and an output terminal.
The signal input terminal is connected to one input terminal of each of the 2-input NAND circuit and the 2-input NOR circuit. The enable signal input terminal is connected to the other input terminal of the 2-input NAND circuit and the signal input terminal of the inverter circuit. The output terminal of the inverter circuit is connected to the other input terminal of the 2-input NOR circuit. The output terminal of the 2-input NAND circuit is connected to the gate electrode of the PMOS transistor, while the output terminal of the 2-input NOR circuit is connected to the gate electrode of the NMOS transistor. The PMOS transistor is connected between the power supply terminal (3 V) and the output terminal. The N-well in the substrate of the PMOS transistor is connected to the 3 V power supply terminal. The NMOS transistor is connected between the ground terminal and the output terminal, while the substrate of NMOS transistor (P-well) is connected to the ground terminal.
The operation of this circuit will now be described. First of all, when an ‘L’ level signal (0 V) is inputted to the enable signal input terminal as an input signal, the output of the 2-input NAND circuit becomes an ‘H’ level and the output of the 2-input NOR circuit becomes an ‘L’ level. Accordingly, the PMOS transistor and the NMOS transistor are turned off. As a result, the output terminal is in a floating state totally unrelated to an input signal to the signal input terminal.
Next, when an ‘H’ level signal is input to the enable signal input terminal as an input signal, if an ‘L’ level signal is input to the signal input terminal the PMOS transistor is turned off and the NMOS transistor is turned on. As a result, the output terminal outputs an ‘L’ level signal. On the other hand, if an ‘H’ level signal is input to the signal input terminal, the PMOS transistor is turned on and the NMOS transistor is turned off. As a result, the output terminal outputs an ‘H’ level signal.
However, in the conventional output circuit, when the output terminal is connected to an external element having a power supply voltage higher than 3 V, for example a bus etc. supplying signals of 5 V, there are circumstances in which the 5 V voltage can be applied to the output terminal while the output terminal is in the floating state. If a 5 V voltage is applied to the output terminal, the drain (P active) of the PMOS transistor becomes 5 V. Because the substrate (N-well) of this PMOS transistor is connected to the 3 V power supply terminal, the diode across the drain (P active) and the substrate (N-well) is forward biased, and so current flows in this diode across the drain and the substrate. This means that if a voltage of 5 V is applied to the output terminal due to the influence of the bus etc. having a 5 V signal supplied to it, there is a possibility of leakage current of a number of mA flowing in the path from the bus supplied with a 5 V signal, to the output terminal, to the drain of the PMOS transistor, to the substrate of the PMOS transistor, to power supply terminal of the output circuit.
OBJECTS OF THE INVENTION
Accordingly, an object of the present invention is to provide an output circuit, in which a leak current can be prevented even if an external supply voltage that is higher than an internal supply voltage is applied to an output terminal.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, an output circuit includes an output terminal (OUT) connected to an external circuit; an internal power supply terminal (VDD); a first node (FL) in a floating state; a second node (
30
); a third node (
37
); a first MOS transistor (P
8
); and a second MOS transistor (P
1
). The first MOS transistor (P
8
) includes a first terminal connected to the internal power supply terminal (VDD), a second terminal connected to the output terminal (OUT), a gate connected to the second node (
30
) and a substrate terminal connected to the first node (FL). The second MOS transistor (P
1
) includes a gate connected to the internal power supply terminal (VDD), a first terminal connected to the second node (
30
), a second terminal connected to the third node (
37
) and a substrate terminal connected to the first node (FL).
According to a second aspect of the present invention, an output circuit includes an output terminal (OUT) connected to an external circuit; an internal power supply terminal (VDD); a first node (FL) in a floating state; a second node (
30
); a third node (
37
); a first MOS transistor (P
8
); a seventh MOS transistor (P
3
); and an eighth MOS transistor (P
4
). The first MOS transistor (P
8
) having a first terminal connected to the internal power supply terminal (VDD), a second terminal connected to the output terminal (OUT), a gate connected to the second node (
30
) and a substrate terminal connected to the first node (FL). The seventh MOS transistor (P
3
) having a first terminal connected to the second node (
30
), a second terminal connected to the first node (FL) and a substrate terminal connected to the first node (FL). The eighth MOS transistor (P
4
) having a gate connected to the third node (
37
), a first terminal connected to the second terminal of the third MOS transistor (P
3
), a second terminal connected to the first node (FL) and a substrate terminal connected to the first node (FL).
According to a third aspect of the present invention, an output circuit includes an output terminal (OUT) connected to an external circuit; an internal power supply terminal (VDD); a first node (FL) in a floating state; a second node (
30
); a third node (
37
); a first MOS transistor (P
8
); a second MOS transistor (P
1
); a seventh MOS transistor (P
3
); and an eighth MOS transistor (P
4
). The first MOS transistor (P
8
) has a first terminal connected to the internal power supply terminal (VDD), a second terminal connected to the output terminal (OUT), a gate connected to the second node (
30
) and a substrate terminal connected to the first node (FL). The second MOS transistor (P
1
) has a gate connected to the internal power supply terminal (VDD), a first terminal connected to the second node (
30
), a second terminal connected to the third node (
37
) and a substrate terminal connected to the first node (FL). The seventh MOS transistor (P
3
) having a first terminal connected to the second node (
30
), a second terminal connected to the first node (FL) and a substrate terminal connected to the first node (FL). The eighth MOS transistor (P
4
) having a gate connected to the third node (
37
), a first terminal connected to the second terminal of the third MOS transistor (P
3
), a second terminal connected to the first node (FL) and a substrate terminal connected to the first node (FL).
REFERENCES:
patent: 5300832 (1994-04-01), Rogers
patent: 5418476 (1995-05-01), Strauss
patent: 5444397 (1995-08-01), Wong et al.
patent: 5546020 (1996-08-01), Lee et al.
patent: 5990705 (1999-11-01), Lim
patent: 6040711 (2000-03-01), Airaksinen et al.
patent: 6078197 (2000-06-01), Kawano
patent:
OKI Electric Industry Co., Ltd.
Tran Toan
Volentine & Francos, PLLC
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