Input/output checker for a memory array

Details Input/output checker for a memory array Input/output checker for a memory array

1994-05-23

1995-10-17

Beausoliel, Jr., Robert W.

Excavating

3649644, 3649643, 3642435, G11C 2900

Patent

active

054597331

ABSTRACT:
A memory array such as an EPROM device includes circuitry that permits testing of a I/O portion of the device without writing data to the EPROM. A data program block that applies a data dependent high voltage pulse to a selected column line for programming can be set to programming or test mode. In the normal, or programming mode, the data input to the data program block is output to the EPROM memory array as is normally required to write to the device. In the test mode, the data output from the data program block controllably connects or decouples the array input line to ground depending upon a binary state of the the input signal. A test output is evaluated using the same sense amp used to evaluate data read from a memory cells of the EPROM array during normal read operations. To prevent writing to the memory cells of the memory array during test, the programming voltage supply is prevented from being applied to a selected column line and all rows in the memory array are deselected simultaneously.

REFERENCES:
patent: 4267583 (1981-05-01), Suzuki
patent: 4701886 (1987-10-01), Sakakibara et al.
patent: 4858190 (1989-08-01), Yamaguchi et al.
patent: 4879688 (1989-11-01), Turner et al.
patent: 4882702 (1989-11-01), Struger et al.
patent: 4969121 (1990-11-01), Chan et al.
Pawlowski, M., et al., "Functional Testing of EPROM's" IEEE J. of Solid-State Circuits, 19(2):212-218 (1979).
Kondo, R., "Test Patterns for EPROMS" IEEE J. of Solid-State Circuits 14(4):730-734 (1979).
Kondo, R., et al., "An Erase Model in Double Poly-Si Gaten-Channel FAMOS Devices" IEEE Transactions on Electron Devices, 25(3):369-374 (1978).
Yu, P. N., "Bitmapping: A Tool for EPROM Failure Analysis", IPFA Symposium Proceeds pp. 32-37 (1987).
Morandi, C., et al., "On the Use of Matrix Algebra for the Description of EPROM Failures"., IEEE J. of Solid-State Circuits 16(2):107-109 (1981).
Suk, D. S., et al., "A March Test for Functional Faults in Semiconductor Random Access Memories", IEEE Transactions on Computers, 30(12):982-985 (1981).
Fuchs, W. K. et al., "A Unified Approach to Concurrent Error Detection in Highly Structured Logic Arrays" IEEE pp. 4-9 (1984).
Sridhar, T., "A New Parallel Test Approach for Large Memories" IEEE, Paper 13.5 pp. 462-470 (1985).
Marinescu, M., "Simple and Efficient Algorithms for Functional RAM Testing", IEEE Paper 10.2 pp. 236-239 (1982).
Mak, G. P., et al., "The Design of Plas with Concurrent Error Detection", pp. 303-310 (1982).
Cocking, J., "Ram Test Patterns and Test Strategy", pp. 1-7.
Barnes, J. J., et al., "Operation and Characterization of N-channel EPROM Cells" Solid-State Electronics, 21:521-529 (1978).
"Random Access Memory" pp. 355-362.
Pawlowski et al., "Functional Testing of EPROMs", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 2, Apr., 1984.
Fuchs, et al., "A Unified Approach to Concurrent Error Detection in Highly Structured Logic Arrays", 16th FTCS, Kissemmee, USA, 1984.
Marinescu, "Simple and Efficient Algorithms for Functional RAM Testing," 1985 Test Conference.
CMS Subsystem Design, pp. 355-362.

Affiliated with

Also associated with

Rating

Input/output checker for a memory array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Input/output checker for a memory array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input/output checker for a memory array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-603580