Input/output cache with mapped pages allocated for caching direc

Details Input/output cache with mapped pages allocated for caching direc Input/output cache with mapped pages allocated for caching direc

1992-12-28

1993-11-16

Dixon, Joseph L.

Boots, shoes, and leggings

364243, 364DIG1, G06F 1208, G06F 1300

Patent

active

052631427

ABSTRACT:
An I/O cache is provided to a computer system comprising a main memory and a number of DVMA/DMA I/O devices for caching I/O data between the main memory and the DVMA/DMA I/O devices. The I/O cache selectively caches the I/O data in accordance to the device class types of the DVMA/DMA devices. The I/O cache comprises an I/O cache data array, an I/O cache address tag array, an I/O cache mapper, and I/O cache control logic. The I/O cache data array comprises a number I/O cache lines, each having a number of I/O cache blocks, for storing I/O data between the main memory and the DVMA/DMA devices. The I/O cache tag comprises a number of corresponding I/O cache address tag entries, each having a number of I/O cache address tags and associated control information, for storing address and control information for the I/O data stored in the I/O cache lines. The I/O cache mapper maps the dynamically or statically allocated I/O buffers in main memory of each DVMA/DMA device having a cacheable device class type to a set of dynamically or statically assigned unique I/O cache buffers in the I/O cache data array, thereby ensuring that no two DVMA/DMA devices with cacheable I/O data will share the same I/O cache block. The I/O control logic controls accesses, indexes and updates to the I/O cache mapper, the I/O cache tag and data arrays.

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80386 A programming and Design Handbook (2nd edition), Penn Brumm and Don Brumm (Authors), 1989, Chapters 4 and 13.

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