Input/output buffer with overcurrent protection circuit

Details Input/output buffer with overcurrent protection circuit Input/output buffer with overcurrent protection circuit

1999-12-29

2001-07-10

Leja, Ronald W. (Department: 2831)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

Reexamination Certificate

active

06259588

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to input/output (I/O) buffers for an integrated circuit, and specifically provides for an overcurrent protection circuit which can be incorporated with an I/O buffer for a Field Programmable Gate Array (FPGA) wherein short circuits can be detected and the output current limited so as to avoid damaging the device. I/O buffers constructed in accordance with the present overcurrent protection circuit are also applicable to hardware logic emulation systems which utilize multiple FPGAs as well as chips other than FPGAs.
BACKGROUND OF THE INVENTION
I/O buffers are used to drive the external pins of integrated circuits. In general, I/O buffers must be capable of sourcing and sinking large amounts of current in order to meet standard specifications and to drive capacitive loads quickly. However, if an I/O pin were to become shorted either to ground, a voltage supply or another pin for more than a few tenths of a second, the integrated circuit may be irreversibly damaged.
If the integrated circuit is a field programmable gate array (FPGA) which can be programmed to implement a wide variety of logic circuit designs, the problem is particularly severe because short circuits may be caused simply by loading the wrong device configuration pattern. The most common failure in an FPGA arises from “pin contention,” where two or more driver circuits are each driving the same board trace but one (or more) is (are) driving a logic high while the other(s) is (are) driving a logic low. If this condition lasts only a few tens of microseconds, there will not be any harm done. However, if the condition persists for several milliseconds, the temperature of the I/O buffer rises to a dangerous level and parasitic bipolar circuit elements in the I/O buffer may begin to conduct. If one of these parasitic bipolar elements goes into second bipolar breakdown (current hogging) then the concentration of power dissipation in a very small region results in permanent thermal damage to the I/O buffer.
Therefore, while it is desirable to be able to limit current, most I/O buffers do not do so because of the difficulty in directly measuring current through a CMOS transistor.
It is accordingly an object of this invention to provide an indirect yet simple method of detecting an overcurrent condition by comparing input and output voltage levels and limit output current accordingly.
It is a further object of this invention to determine if an overcurrent error condition exists by monitoring this overcurrent detection for a predetermined period of time, with or without the use of an external clock signal.
It is a further object of this invention to provide a mechanism for limiting the output current if the overcurrent error condition exists.
It is still further an object of this invention to provide a means of controlling the overcurrent circuitry and signaling the occurrence of an overcurrent error condition.
SUMMARY OF THE INVENTION
These and other objects of the present invention are achieved with an overcurrent protection circuit which indirectly detects an overcurrent condition by comparing the voltage on a pin to the logic level which the I/O buffer is trying to drive. If the two levels are different for more than a predetermined time, thus signifying an overcurrent error condition, then the large primary output driver is turned off to limit the output current. A small secondary driver remains on so that the correct logic level will be restored when the short is removed. When a short is detected, a latch is set which can be read through a JTAG port to determine the location of the short. An interrupt signal is also generated to alert the user that a short has occurred. FPGAs have not yet incorporated such overcurrent protection circuits.


REFERENCES:
patent: Re. 34444 (1993-11-01), Kaplinsky
patent: 4293783 (1981-10-01), Patil
patent: 4825414 (1989-04-01), Kawata
patent: 4855958 (1989-08-01), Ikeda
patent: 4884165 (1989-11-01), Kong et al.
patent: 4893280 (1990-01-01), Gelsomini et al.
patent: 4896244 (1990-01-01), Kalina
patent: 4963770 (1990-10-01), Keida
patent: 4975601 (1990-12-01), Steele
patent: 5042004 (1991-08-01), Agrawal et al.
patent: 5122685 (1992-06-01), Chan et al.
patent: 5212666 (1993-05-01), Takeda
patent: 5231312 (1993-07-01), Gongwer et al.
patent: 5276842 (1994-01-01), Sugita
patent: 5313119 (1994-05-01), Cooke et al.
patent: 5315178 (1994-05-01), Snider
patent: 5329460 (1994-07-01), Agrawal et al.
patent: 5329493 (1994-07-01), Meyer et al.
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5352940 (1994-10-01), Watson
patent: 5375089 (1994-12-01), Lo
patent: 5384500 (1995-01-01), Hawes et al.
patent: 5386155 (1995-01-01), Steele et al.
patent: 5408434 (1995-04-01), Stansfield
patent: 5412260 (1995-05-01), Tsui et al.
patent: 5414377 (1995-05-01), Freidin
patent: 5426378 (1995-06-01), Ong
patent: 5530670 (1996-06-01), Matsumoto
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5566123 (1996-10-01), Freidin et al.
patent: 5572148 (1996-11-01), Lytle et al.
patent: 5596742 (1997-01-01), Agarwal et al.
patent: 5668771 (1997-09-01), Cliff et al.
patent: 5717901 (1998-02-01), Sung et al.
patent: 5796267 (1998-08-01), Pederson
patent: 5809281 (1998-09-01), Steele et al.
patent: 5835405 (1998-11-01), Tsui et al.
patent: 5852608 (1998-12-01), Csoppenszky et al.
patent: 0081917 (1983-08-01), None
patent: 0 225 715 (1987-06-01), None
patent: 0410759 A2 (1991-01-01), None
patent: 0415542 A2 (1991-03-01), None
patent: 0420389 A1 (1991-04-01), None
patent: 0507507 A2 (1992-10-01), None
patent: 0530985 A2 (1993-03-01), None
patent: 0569137 A2 (1993-11-01), None
patent: 01091525 (1989-04-01), None
patent: 01091526 (1989-04-01), None
patent: 95/15152 (1992-09-01), None
patent: WO 94/10754 (1994-05-01), None
Masumoto, Rodney T., “Configurable On-Chip RAM Incorporated into High Speed Logic Array,” IEEE Custom Integrated Circuits conference, Jun. 1985, CH2157-6/85/0000-0240, pp. 240-243.
Landry, Steve, “Application-Specific ICs, Relying on RAM, Implement Almost Any Logic Function,” Electronic Design, Oct. 31, 1985, pp. 123-130.
Bursky, Dave, “Shrink Systems with One-chip Decoder, EPROM, and RAM,” Electronic Design, Jul. 28, 1988, pp. 91-94.
Kawana, Keiichi et al., “An Efficient Logic Block Interconnect Architecture for User-Reprogrammable Gate Array,” IEEE 1990 Custom Integrated Circuits Conf., May 1990, CH2860-5/90/0000-0164, pp. 31.3.1 to 31.3.4.
Shubat, Alexander et al., “A Family of User-Programmable Peripherals with a Functional Unit Architecture,” IEEE Jor. of Solid-State Circuits, vol. 27, No. 4, Apr. 1992, 0018-9200/92403.00, pp. 515-529.
“AT&Ts Orthogonal ORCA Targets the FPGA Future,” 8029 Electronic Engineering, 64, No. 786, Jun. 1992, pp. 9-10.
Burskey, Dave, “FPGA Advances Cut Delays, Add Flexibility,” 2328 Electronic Design, 40, No. 20, Oct. 1, 1992, pp. 35-43.
Smith, Daniel, “Intel's FLEXlogic FPGA Architecture,” IEEE 1063-6390/93, 1993 pp. 378-384 No Month.
Bursky, Dave, “Denser, Faster FPGAs Vie for Gate-Array applications,” 2328 Electronic Design, 41, No. 11, May 27, 1993, pp. 55-75.
Ngai, Kai-Kit Tony, “An SRAM-Programmable Field-Reconfigurable Memory,” University of Toronto, Canada, Jun. 1994, UMI Dissertation Services, pp. 1-68.
Kautz, “Cellular Logic in Memory Arrays,” IEEE Trans on Computers, vol. C-18, No. 8, Aug. 1969, pp. 719-727.
Stone, “A Logic in Memory Computer,” IEEE Trans. on Computers, Jan. 1970, pp. 73-78.
Manning, “An Approach to Highly Integrated Computer Maintained Cellular Arrays,” IEEE Trans. on Computers, vol. C-26, No. 67, Jun. 1977, pp. 536-552.
Patil et al., “A Programmable Logic Approach for VLSI,” IEEE Trans. on Computers, vol. C-28, No. 9, Sep. 1979, pp. 594-601.
Seitz, “Concurrent VLSI Architectures,” IEEE Trans. on Computers, vol. C-33, No. 12, Dec. 1984, pp. 1247-1265.
Hsieh et al., “Third Generation Architecture Boosts Speed and Density of Field Programmable Gate Arrays,” Proc. of IEEE CICC Conf., May 1990, pp. 31.2.1 to 31.2.7.
Bursky, “Combination RAM/PLD Opens New Application Options,” Electr

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