Input/output buffer with overcurrent protection circuit

Details Input/output buffer with overcurrent protection circuit Input/output buffer with overcurrent protection circuit

1997-07-16

2000-03-07

Leja, Ronald W.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

H02H 300

Patent

active

060348577

ABSTRACT:
An overcurrent protection circuit for input/Output (I/O) buffers for a Field Programmable Gate Array wherein short circuits can be detected and the output current limited so as to avoid damaging the device. I/O buffers having the overcurrent protection circuit can detect a contention between the buffers. In order to eliminate the contention, certain I/O buffers will go into a noncontending state.

REFERENCES:
patent: Re34444 (1993-11-01), Kaplinsky
patent: 4293783 (1981-10-01), Patil
patent: 4825414 (1989-04-01), Kawata
patent: 4855958 (1989-08-01), Ikeda
patent: 4884165 (1989-11-01), Kong et al.
patent: 4893280 (1990-01-01), Gelsomini et al.
patent: 4896244 (1990-01-01), Kalina
patent: 4963770 (1990-10-01), Keida
patent: 4975601 (1990-12-01), Steele
patent: 5042004 (1991-08-01), Agrawal et al.
patent: 5122685 (1992-06-01), Chan et al.
patent: 5212666 (1993-05-01), Takeda
patent: 5231312 (1993-07-01), Gongwer et al.
patent: 5256914 (1993-10-01), Boomer
patent: 5276842 (1994-01-01), Sugita
patent: 5313119 (1994-05-01), Cooke et al.
patent: 5315178 (1994-05-01), Snider
patent: 5329460 (1994-07-01), Agrawal et al.
patent: 5329493 (1994-07-01), Meyer et al.
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5352940 (1994-10-01), Watson
patent: 5375089 (1994-12-01), Lo
patent: 5384500 (1995-01-01), Hawes et al.
patent: 5386155 (1995-01-01), Steele et al.
patent: 5408434 (1995-04-01), Stansfield
patent: 5412260 (1995-05-01), Tsui et al.
patent: 5414377 (1995-05-01), Freidin
patent: 5426378 (1995-06-01), Ong
patent: 5530670 (1996-06-01), Matsumoto
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5566123 (1996-10-01), Freidin et al.
patent: 5572148 (1996-11-01), Lytle et al.
patent: 5596742 (1997-01-01), Agarwal et al.
patent: 5668771 (1997-09-01), Cliff et al.
patent: 5809281 (1998-09-01), Steele et al.
patent: 5852608 (1998-12-01), Csoppenszky et al.
patent: 5935405 (1998-11-01), Tsui et al.
Masumoto, Rodney T., "Configurable On-Chip RAM Incorporated into High Speed Logic Array," IEEE Custom Integrated Circuits Conference, Jun. 1985, CH2157-6/85/0000-0240, pp. 240-243.
Landry, Steve, "Application -Specific ICs, Relying on RAM, Implement Almost Any Logic Function," Electronic Design, Oct. 31, 1985, pp. 123-130.
Bursky, Dave, "Shrink Systems with One-Chip Decoder, EPROM, and RAM," Electronic Design, Jul. 28, 1988, pp. 91-94.
Kawana, Keiichi et al., "An Efficient Logic Block Interconnect Architecture for User-Reprogrammable Gate Array," IEEE 1990 Custom Integrated Circuits Conf., May 1990, CH2860-5/90/0000-0164, pp. 31.3.1 to 31.3.4.
Shubat, Alexander et al., "A Family of User-Programmable Peripherals with a Functional Unit Architecture," IEEE Jor. of Solid-State Circuits, vol. 27, No. 4, Apr. 1992, 0018-9200/92$03.00, pp. 515-529.
"AT&T's Orthogonal ORCA Targets the FPGA Future," 8029 Electronic Engineering, 64, No. 786, Jun. 1992, pp. 9-10.
Bursky, Dave, "FPGA Advances Cut Delays, Add Flexibility," 2328 Electronic Design, 40, No. 20, Oct. 1, 1992, pp. 35-43.
Smith, Daniel, "Intel's FLEXlogic FPGA Architecture," IEEE 1063-6390/93, 1993 pp. 378-384.
Bursky, Dave, "Denser, Faster FPGAs Vie for Gate-Array Applications," 2328 Electronic Design, 41, No. 11, May 27, 1993, pp. 55-75.
Ngai, Kai-Kit Tony, "An SRAM-Programmable Field-Reconfigurable Memory," University of Toronto, Canada, Jun. 1994, UMI Dissertation Services, pp. 1-68.
Kautz, "Cellular Logic in Memory Arrays," IEEE Trans. on Computers, vol. C-18, No. 8, Aug. 1969, pp. 719-727.
Stone, "A Logic in Memory Computer," IEEE Trans. on Computers, Jan. 1970, pp. 73-78.
Manning, "An Approach to Highly Integrated Computer Maintained Cellular Arrays," IEEE Trans. on Computers, vol. C-26, No. 6, Jun. 1977,pp. 536-552.
Patil et al., "A Programmable Logic Approach for VLSI," IEEE Trans. on Computers, vol. C-28, No. 9, Sep. 1979, pp. 594-601.
Seitz, "Concurrent VLSI Architectures," IEEE Trans. on Computers, vol. C-33, No. 12, Dec. 1984, pp. 1247-1265.
Hsieh et al., "Third Generation Architecture Boosts Speed and Density of Field Programmable Gate Arrays," Proc. of IEEE CICC Conf., May 1990, pp. 31.2.1 to 31.2.7.
Bursky, "Combination RAM/PLD Opens New Application Options," Electronic Design, May 23, 1991, pp. 138-140.
Ling et al., "WASMII: A Data Driven Computer on a Virtual Hardware," Proc. of IEEE Field Prog. Custom Computing Machines Conf., Napa, California, Apr. 1993, pp. 33-42.
Casselman, "Virtual Computing and The Virtual Computer," IEEE, Jul. 1993, p. 43.
Quenot et al., "A Reconfigurable Compute Engine for Real-Time Vision Automata Prototyping," Proc. of IEEE FCCM Conf., Napa, California, Feb. 1994, pp. 91-100.
Plus Logic "FPSL5110 Intelligent Data Buffer" Product Brief, Plus Logic, Inc., San Jose, California, Oct. 1990, pp. 1-6.
Intel Preliminary Datasheet, "iFX780: 10ns FLEXlogic FPGA with SRAM Option," Nov. 1993, pp. 2-24 to 2-46.
Quinnell, Richard A., "FPA Family Offers Speed, Density, On-chip RAM, and Wide-Decoder Logic," EDN Dec. 6, 1990, pp. 62-63.
Satoh, Hisayasu et al., "A 209K-Transistor ECL Gate Array with RAM," IEEE Jor. of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1275-1279.
U.S. Pat. App. S.N. 08/607,849 filed Feb. 27, 1996 now US Pat. 5,796,267.
U.S. Pat. App. S.N. 08/555109, filed Nov. 8, 1995 now US Pat. 5,717,901.
Altera Brochure, 1995 Data Book, Flex 8000 Programmable Logic Device Family, pp. 52-55 No Month.
Schematic of a Tristate Input/Output Buffer used in Quickturn's Enterprise System 1992, No Month.

Affiliated with

Also associated with

Rating

Input/output buffer with overcurrent protection circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Input/output buffer with overcurrent protection circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input/output buffer with overcurrent protection circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-368937