Input/output buffer protection circuit

Details Input/output buffer protection circuit Input/output buffer protection circuit

2006-05-16

2006-05-16

Easthom, Karl (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S091100, C361S093100, C361S111000

Reexamination Certificate

active

07046493

ABSTRACT:
An input/output buffer protection circuit, which comprises an I/O pad, an I/O buffer, an n-well control circuit, a gate control circuit, and a protection component. The I/O buffer includes a PMOS transistor and a NMOS transistor. The n-well control circuit is coupled to an n-well of the PMOS transistor. When an input voltage higher than a source voltage is applied, voltage at the n-well of the PMOS is increased by the n-well control circuit to the input voltage level. The gate control circuit is coupled to the gate terminal of the PMOS transistor and the input/output pad. When an input voltage higher than a source voltage is applied, voltage at the gate terminal of the PMOS is increased by the gate control circuit to the source voltage level. Wherein the gate control circuit comprises a transistor and the transistor transfers a high potential control voltage to the gate of the PMOS transistor in output mode. The protection component is coupled between the gate of the transistor and the I/O pad to generate a voltage drop down path and block the I/O pad signal from flowing back to the gate of the transistor.

REFERENCES:
patent: 6084431 (2000-07-01), Shigehara et al.

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