Input/output buffer circuit for semiconductor integrated circuit

Details Input/output buffer circuit for semiconductor integrated circuit Input/output buffer circuit for semiconductor integrated circuit

1992-01-16

1993-12-14

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 3072968, 307482, H03K 19092, H03K 1901

Patent

active

052705897

ABSTRACT:
This invention provides an input/output buffer circuit which allows input/output interfacing with another device designed to output a signal having a voltage level higher than that of the supply voltage of the semiconductor integrated circuit, and prevents the formation of an input leakage current path. An NMOS transistor is inserted between the input/output pad of the semiconductor integrated circuit and the output node of an output buffer circuit. The input node of an input buffer circuit is directly connected to the output node of the output buffer circuit or is connected to the input/output pad through another) NMOS transistor. If a transistor having a low threshold value is used as this NMOS transistor, a potential having the same level as that of the supply potential is applied to its gate. If a transistor is used, a potential having a level higher than the supply potential is applied to its gate.

REFERENCES:
patent: 3983543 (1976-09-01), Cordaro
patent: 4306163 (1981-12-01), Blume, Jr. et al.
patent: 4313064 (1982-01-01), Claude
patent: 4479067 (1984-10-01), Fujita
patent: 4703198 (1987-10-01), Porter et al.
patent: 4835684 (1989-05-01), Kanai
patent: 5177573 (1993-01-01), Ukita et al.

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