Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-11-30
2003-06-03
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S112000
Reexamination Certificate
active
06573765
ABSTRACT:
TECHNICAL FIELD
The present invention is related generally to integrated circuits, and more particularly, to input-output (I/O) buffer circuits for an integrated circuit.
BACKGROUND OF THE INVENTION
Semiconductor devices often include data pins that serve both input and output (I/O) functions. That is, a data pin, which is internally connected to a pad on the semiconductor device, must be able to provide data signals at an adequate voltage and slew rate to, as well as receive data signals from, a bus to which the data pin is coupled. Moreover, when data is not being provided from or received by the data pin, it should appear as an open circuit in order to avoid pulling down the bus as a current sink. Thus, in order to satisfy these requirements, an I/O buffer circuit included in the semiconductor device should have an input mode where signals applied to the pad are received by the semiconductor device, an output mode where data signals are driven by the buffer circuit having sufficient voltages and transition time, and a tristate mode where the pad is effectively in a high impedance state.
Typical I/O buffer circuits include a PMOS pull-up transistor for the purposes of driving high output data signals. Unlike output buffers using NMOS pull-up transistors, a boot circuit providing a super-voltage to the gate of the pull-up transistor is not required for the full voltage of a supply voltage to be provided for a high output signal. The PMOS pull-up transistor is typically formed in an n-well to facilitate the use of CMOS technology in forming NMOS pull-down transistors for the I/O buffer circuit. However, as a result of the PMOS pull-up transistor being formed in an n-well, when an I/O buffer in input mode receives an input signal having a voltage that sufficiently exceeds the supply voltage, current may be drawn through the PMOS pull-up transistor to the voltage supply as a result of the formation of parasitic diodes and/or inadvertent channel conduction. As the pull-up transistor becomes conductive, the voltage supply coupled to the pull-up transistor behaves as a current sink for the input signal, potentially pulling down the voltage of the input signal and consuming drive current. Where the current consumption is severe, the circuit driving the input signal will not be able to sustain an adequate voltage level for the input signal, resulting in the input signal being read incorrectly.
The situation where the voltage of the input signal exceeds the supply voltage may occur where a relatively low voltage semiconductor device is connected with a bus using higher voltage values. For example, a semiconductor device may have an operating voltage of 3.3 V, but is coupled to a data bus providing data signals having voltages as high as 5.0 V. Moreover, the I/O buffer of the semiconductor device should be designed to accommodate signal fluctuations, in some cases, the voltage of the input signal may reach as high as 5.5 V. In these cases, the voltage of the input signal applied to the pad of the semiconductor device may be great enough to cause the PMOS pull-up transistor of the I/O buffer circuit to conduct.
Moreover, where lower voltage devices are connected to a higher voltage bus, the voltage that may be potentially applied across the transistor may exceed the node-to-node technology voltages limits for the various transistors in the I/O buffer circuit. When node-to-node voltages exceed the technology limits, the transistor may be irreparably damaged. For example, some node-to-node voltage limits for a typical pull-up transistor are: Vgs, gate-source max.=5 V, Vgd, gate-drain max.=5 V, Vgb, gate-bulk max.=5 V, Vds, drain-source max.=4 V, Vdb, drain-bulk max.=7 V, Vsb, source-bulk max.=7 V. As previously discussed, applications of a lower voltage semiconductor device with higher voltage busses may result in node-to-node voltages as high as 5.5 V, thus, exceeding several of the node-to-node voltage limits of the transistor. Where the transistor is irreparably damaged, the I/O buffer circuit may no longer be operational. As a result, I/O buffer circuits have been designed that can accommodate coupling to a bus providing relatively higher voltage data signals, and prevent the transistors of the I/O buffer circuit from being damaged when the voltage of an input signal is sufficient to cause the node-to-node voltage limits of the transistors to be exceeded. One approach to avoiding parasitic diode conduction is to include an additional PMOS transistor coupled between the n-well in which the PMOS pull-up transistor is formed and the voltage supply. The gate of the additional PMOS transistor is coupled to the I/O pad. As the voltage of the input signal applied to the I/O pad exceeds the supply voltage, the n-well is disconnected and left floating to be charged to approximately the voltage of the input signal. Although current is not drawn through the parasitic diodes to the voltage supply, charging the n-well to a relatively high voltage may lead to latch-up problems.
An approach that has been taken to prevent PMOS channel conduction when an input signal having a voltage greater than the supply voltage is to include a gate control block that includes what is essentially a voltage level shifter to drive the gate of the PMOS pull-up transistor during the input mode with a relatively high voltage, such as 5.0 volts. Thus, when an input signal having a voltage greater than the supply voltage is received by the I/O buffer, but less than (5.0V−|Vtpull-up|), where Vtpull-up is the MOS conduction threshold voltage, inadvertent channel conduction is prevented. Although the PMOS pull-up transistor is held in an OFF state, this approach does require a high voltage supply, or additional circuitry to generate the elevated voltage necessary to prevent channel conduction. Where space requirements on a device are limited, the addition of the gate control block may not be an acceptable solution.
Therefore, there is a need for an I/O buffer circuit that, when the input voltage exceeds the supply voltage, prevents inadvertent diode and channel conduction in the PMOS pull-up transistor, and prevents the node-to-node technology voltage limits from being exceeded.
SUMMARY OF THE INVENTION
The invention is directed to an I/O buffer having a pull-up transistor and which avoids inadvertent conduction when an input signal having a voltage greater than the supply voltage is applied to the I/O buffer while in an input mode. The input buffer includes a driver circuit having pull-up and pull-down transistors connected in series, and an I/O node located between the transistors to receive an input signal. A pull-up transistor bias circuit is also included in the I/O buffer. The bias circuit has a low source terminal coupled to a voltage supply, a high source terminal coupled to the I/O node, and a bias terminal coupled to the gate and body of the pull-up transistor to provide a voltage sufficient to avoid inadvertent conduction. While the I/O buffer is set in the input mode, and the voltage of the input signal is less than a voltage threshold, the bias circuit applies the voltage of the voltage supply to the gate and body of the pull-up transistor. However, when the voltage of the input signal exceeds the voltage threshold, the bias circuit applies the voltage of the input signal to the gate and body of the pull-up transistor to prevent inadvertent conduction.
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Dabral S. et al., “Basic ESD and I/O Design”, New York, A Wiley Interscience Publication, John Wiley & Sons, Inc., 1998. pp. 260-266.
Bales Timothy
Hunt Ken
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