Input optimized FET bias circuit

Details Input optimized FET bias circuit Input optimized FET bias circuit

1980-01-29

1982-03-16

Mullins, James B.

Amplifiers

With semiconductor amplifying device

Including field effect transistor

330289, 330296, H03F 316

Patent

active

043203523

ABSTRACT:
A field effect transistor bias circuit is presented which exhibits a low impedance for small signals and a high impedance for large signals. This circuit uses an operational amplifier to provide a temperature compensated low impedance voltage source for the gate bias which is optimal for small signal operation. In the presence of a large signal, the gate begins to draw current. This causes the operational amplifier to saturate and transforms the bias circuit into a high impedance source, which is optimal for large signal operation.

REFERENCES:
patent: 4011518 (1977-03-01), Irvine et al.
patent: 4077013 (1978-02-01), Morez et al.
patent: 4123722 (1978-10-01), Cubbison, Jr.
patent: 4152666 (1979-05-01), Kajikawa et al.

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