Input gate protection circuit and method

Details Input gate protection circuit and method Input gate protection circuit and method

2002-08-01

2004-07-27

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

06768618

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of electronic circuits and methods and more particularly to an input gate protection circuit and method.
BACKGROUND OF THE INVENTION
In modern integrated circuits it is common for a portion of the circuit to use one voltage range and a second portion of the circuit to use a second voltage. For instance, the input signal may have a range of 3.3 volts and the core portion of the circuit may operate at a nominal voltage of 2.5 volts. This presents challenges when a signal from one portion of the circuit needs to be received by the second portion of the circuit. One prior art solution has been to use a NMOS (n-metal oxide silicon) transistor to pass the high voltage signal to a signal shaping device such as an inverter. The inverter shapes the input signal and converts it to the desired signal levels. The pass transistor limits the voltage applied to the inverter. The pass transistor is a low voltage transistor and it is a general design goal to use low voltage devices. The pass transistor's gate is connected to the power supply of the second portion of the circuit or second voltage source. When no power is applied to the second portion of the circuit, the source to gate voltage of the pass transistor is equal to the high voltage and stresses the gate oxide of the pass transistor. This results in degradation of the pass transistor over time.
Thus there exists a need for a circuit and method that does not result in gate oxide stress when no power is applied to the low voltage portion of a circuit.
SUMMARY OF THE INVENTION
An input gate protection circuit that overcomes these problems has a pass transistor having a source coupled to an input signal. A first voltage range control circuit is coupled to a gate of the pass transistor. A second voltage range control circuit is coupled to the gate of the pass transistor. When power is not applied to the second portion of the circuit and the second voltage range control circuit, the first voltage range control circuit limits the voltage applied to the gate oxide of the pass transistor. In one embodiment an input shaping device has an input coupled to a drain of the pass transistor.
In one embodiment the first voltage range control circuit has a diode coupled between the input signal and the gate of the pass transistor. In another embodiment, the first voltage range control circuit has a pair of diodes coupled between the input signal and the gate of the pass transistor. In another embodiment, the input signal has a first voltage range. The first voltage range is 0.0-3.3 volts in one embodiment. The second voltage range is 0.0-1.8 volts, in one embodiment.
In one embodiment, the second voltage range circuit has a transistor coupling the gate of the pass transistor to a second voltage source. The transistor has a gate coupled to the input signal, in one embodiment.
In another embodiment, an input gate protection circuit has a pass transistor with a source coupled to an input signal. A first control circuit is coupled to a gate of the pass transistor. A second control circuit is coupled the gate of the pass transistor. In one embodiment, the first control circuit has an input coupled to the input signal. The first control circuit includes a plurality of diodes, in one embodiment.
In another embodiment, the second control circuit has an input coupled to a second voltage source. The second control circuit includes a transistor with a source coupled to a second voltage source, in one embodiment. The transistor has a drain coupled to the gate of the pass transistor, in one embodiment. the transistor has a gate coupled to the input signal and to the second voltage source, in another embodiment. The transistor is a PMOS transistor, in one embodiment.
A method of operating an input gate protection circuit includes the steps of: a) determining if a second voltage source in on; b) when the second voltage source is not on, attenuating an input signal to form an attenuated signal; and c) applying the attenuated signal to a gate of a pass transistor. When the second voltage source is on, the second voltage source is applied to the gate of the pass transistor. In one embodiment, a peak input voltage of the input signal is greater than a voltage of the voltage source. The voltage source is applied through a controllable switch in one embodiment.
In another embodiment, a diode is coupled between the input signal and the gate of the pass transistor.


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patent: 6034553 (2000-03-01), Kwong
patent: 6049445 (2000-04-01), Gauthier
patent: 6268759 (2001-07-01), Graves

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