Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
2000-12-14
2002-07-02
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
C327S551000
Reexamination Certificate
active
06414540
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to an input filter stage for a data stream, to an I2C bus interface, to an integrated circuit and to a method for filtering a data stream.
During serial data transmission operations, particularly during data transmission via unscreened lines, as in the case of the I2C bus system, for example, interference frequently arises in the signals. This interference is, by way of example, voltage spikes and interference pulses caused by crosstalk or reflection or by electromagnetic influence.
Particularly when no suitable termination of the bus is provided, line reflections are customary in an I2C bus system, in which a changing number of input interfaces can additionally be connected. Furthermore, long line paths can additionally make the bus more difficult to tune if not all of the input stages are located on a printed circuit board.
Input filter stages are used to suppress such interference. The input stages used are frequently Schmitt triggers, which ignore signal fluctuations below or above particular threshold values and therefore pass on only clearly detectable signal level changes to the logic connected downstream. Such circuits are frequently used for “debouncing” keys on keyboards, for example.
However, a Schmitt trigger has the disadvantage that interference pulses and voltage spikes which have amplitude values higher than the signals are rated as signals and are then erroneously passed on to the logic connected downstream.
SUMMARY OF THE INVENTION
It is the object of the invention to provide an input filter stage and a method for filtering a data stream supplied via an input line in which interference, particularly interference pulses and voltage spikes, is reliably filtered out, the aim being for the circuit complexity for the input filter stage to be as low as possible.
This object is achieved by the features specified in the independent claims.
The invention provides an input filter stage for filtering a data stream which has a register chain, which is connected to an input line and has a plurality of series-connected registers, and a switching device connected to an output line and to the register chain in order to switch the output line, a signal input of a first register in the register chain being connected to the input line, and a signal input of a subsequent register in the register chain being connected to a respective signal output of a preceding register in the register chain, a clock input for the plurality of registers being connected to a respective clock line which can be used to transmit a sampling signal at a sampling frequency, the sampling frequency being higher than a maximum data transmission frequency of the data stream, and the switching device being connected to the register chain such that the output line can be switched to a logic level of the signal outputs of the plurality of registers when output signals which are produced at each of the signal outputs of the plurality of registers are at the same logic level.
The essential advantage obtained by the invention over the prior art is that little circuit complexity is used to provide a possibility for suppressing interference on bus lines in data streams, particularly for suppressing interference which occurs as a result of line reflections or crosstalk.
The method disclosed can be applied to any interference-affected signal line which is sampled using a clock whose frequency is higher than the data transmission frequency in the data stream.
In one embodiment of the invention, provision may be made for the plurality of registers each to be in the form of D-type flip-flops in the context of a shift register.
One advantageous development of the invention provides that the register chain comprises three registers, which means that only a minimum level of circuit complexity is required.
Provision is expediently made for the sampling frequency to be a plurality of times higher than the maximum frequency of the data transmission, preferably to be approximately 50 MHz, which improves the quality of the interference elimination.
In one development of the invention, the circuit device comprises an AND gate, a NOR gate and a further register, inputs of the AND gate and of the NOR gate each being connected to the signal output of one of the plurality of registers, and outputs of the AND gate and of the NOR gate each being connected to inputs of the further register. This allows the circuit device to be formed using simple logic gates.
The filter input stage according to the invention may advantageously be used in an I2C bus system or in an integrated circuit.
The method claims, correspondingly, have the advantages cited in the context of the apparatus claims.
In the case of the method, provision may expediently be made for the output line to be switched by means of the SR-type flip-flop, an S-input of the SR-type flip-flop assuming a logic “1” level only when the same logic level of the signal outputs of the registers is a logic “1” level, and an R-input of the SR-type flip-flop assuming a logic “1” level only when the same logic level of the signal outputs of the registers is a logic “0” level.
REFERENCES:
patent: 5001374 (1991-03-01), Chang
patent: 5059834 (1991-10-01), Tago et al.
patent: 5386159 (1995-01-01), Dupre
patent: 5663675 (1997-09-01), O'Shaughnessy
patent: 6211724 (2001-04-01), Kwon
patent: 4220557 (1994-01-01), None
patent: 0664612 (1995-07-01), None
Deutsche Thomson-Brandt GmbH
Kiel Paul P.
Nguyen Linh
Tripoli Joseph S.
Wells Kenneth B.
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