Input EDS protection circuit

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Device protection

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Details

257355, 257154, H01L 2704, H01L 2908, H01L 2952

Patent

active

053369084

ABSTRACT:
The input ESD protection circuit of the present invention uses a series n+ active area resistor placed in an n-well placed in series with shunt transistor all of which are in parallel with an SCR shunt to ground circuit, thereby providing greater than +/-7000V HBM (the Mil. Std. human body model (HBM) test model) and +/-600V MM EIAJ (the EIAJ machine model (MM) test model) ESD protection response. The series n+ active area resistor is placed inside an n-well as are all metal contacts to the input, to improve junction integrity during an ESD event. The parallel SCR circuit is designed in a layout that has an n+ diffusion area tied to V.sub.SS surrounding the n+/p+ diffusion inside the n-well on three sides to provide greater surface area for current distribution.

REFERENCES:
patent: 4400711 (1983-08-01), Avery
patent: 4757363 (1988-07-01), Bohm et al.
patent: 4939616 (1990-07-01), Rountree
patent: 5012317 (1991-04-01), Rountre
patent: 5140401 (1992-08-01), Ker et al.
patent: 5181092 (1993-01-01), Atsumi
patent: 5182220 (1993-01-01), Ker et al.
"A Process-Tolerant Input Protection Circuit for Advanced CMOS Processes", Roundtree et al., 1988 EOS/ESD Symposium Proceedings, pp. 201-205.
"Input Protection Design for Overall Chip Reliability", Duvvury et al., 1989 EOS/ESD Symposium Proceedings, pp. 190-197.

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