Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-09-25
2003-04-08
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S118000, C341S120000
Reexamination Certificate
active
06545626
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to an input delay correction for an interleave type AID (Analog to Digital) converter.
2. Description of the Related Art
With speed-up, for example, of a device under test (DUT), speed-up of an A/D converter for use in conveying an analog signal outputted from the DUT into a digital signal for example has been demanded so far. The interleave type AID converter is for attaining the speed-up of an A/D converter.
An example of an interleave type A/D converter is shown in FIG.
10
. An analog signal outputted from a DUT
102
is inputted to A/D converters
112
and
114
. A sampling clock A is provided to the A/D converter
112
, while a sampling dock B is provided to the A/D converter
114
. The sampling clock B is delayed a half cycle from the sampling clock A. The cycle of the sampling clock A and that of the sampling clock B are both assumed equal to 100 [ns]. The A/D converter
112
outputs digital signals D
0
, D
2
, D
4
, . . . , while the A/D converter
114
outputs digital signals D
1
, D
3
, D
5
, . . . The digital signals outputted from the A/D converters
112
and
114
are outputted as D
0
, D
1
, D
2
, D
3
, D
4
, . . . through a multiplexer
120
.
FIG. 11
is a time chart of an entire sampling clock and the sampling clocks A and B. First, as to the sampling clock A, a clock signal corresponding to D
0
is outputted, then in 100 [ns] after that there is outputted a clock signal corresponding to D
2
, and further in 100 [ns] after that there is outputted a clock signal corresponding to D
4
. As to the sampling clock B, a clock signal corresponding to D
1
is outputted a half cycle, i.e., 50 [ns], later than a clock signal corresponding to D
0
and in 100 [ns] after that there is outputted a clock signal corresponding to D
3
. Thus, as shown at the top stage in
FIG. 11
, the entire sampling clock is a combination of both sampling clocks A and B, i.e., D
0
, D
1
, D
2
, D
3
, D
4
, . . . In this case, the cycle of the entire sampling clock is 50 [ns].
Thus, by using two A/D converters (
112
and
114
), sampling can be done with a half cycle of the ordinary sampling cycle. For example, sampling with a cycle of 100 [ns] can be made into sampling with a cycle of 50 [ns]. More than two A/D converters may be used. If three A/D converters are used, sampling can be done with a one-third cycle, and if four A/D converters are used, sampling can be done with a one-fourth cycle. For example, if four A/D converters are used, sampling with a cycle of 100 [ns] can be made into sampling with a cycle of 25 [ns].
SUMMARY OF INVENTION
However, for reducing the sampling cycle exactly to half, it is necessary that a time lag between the sampling clocks A and B be set exactly at a half cycle. For example, as shown in FIG.
12
(
a
), it is here assumed that the sampling clock B is delayed by &tgr; relative to a time at which it should be. Such a phenomenon is called an input delay. In this case, an entire sampling clock is as shown in FIG.
12
(
b
). The spacing of clock signals corresponding to D
0
, D
1
, and D
2
should be 50 [ns], but, as shown in the same figure, the spacing between clock signals corresponding to D
0
and D
1
is 50+&tgr; [ns], while the spacing between clock signals corresponding to D
1
and D
2
is 50−&tgr; [ns]. It is evident that such non-uniform sampling cycles are inconvenient.
Accordingly, it is an object of the present invention to provide an input delay correcting system, etc. for an A/D converter.
According to an embotiment of the present invention, an input delay correcting system for an A/D converter, operating at the time of receiving an analog signal and outputting a digital signal, the system includes: a plurality of A/D converter unit for converting the analog signal into digital signals in synchronism with a sampling clock signal; a clock signal supply unit which supplies the sampling clock signal in different phases to the A/D converter unit; a delay unit which delays an output of each the A/D converter unit by a time corresponding to a cycle of the sampling clock signal; a multiplier unit which multiplies outputs of the delay unit by predetermined coefficients and which outputs the thus- multiplied signals; a totalizer unit which outputs the total of outputs provided from the multiplier unit; and an alternate output unit which outputs an output of the delay unit and, an output of the totalizer unit in an alternate manner, the output of the delay unit being spaced a predetermined time from a time point at which the output of the totalizer unit takes a maximum value.
According to the thus constructed input delay correcting system for an A/D converter, the delay unit, the multiplier unit and the totalizer unit constitute so called FIR (Finite Impulse Response) filter. Since the timing at which the output of the FIR filter takes a maximum value is constant, even with an input delay found in any of plural A/D converter means, the input delay can be corrected if a signal provided when the output of the FIR filter takes a maximum value is used as digital signal.
According to an embotiment of the present invention, an input delay correcting method for an input delay correcting system for an A/D converter having a plurality of A/D converter unit for converting analog signal into digital signals in synchronism with a sampling clock signal; and, a clock signal supply unit which supplies the sampling clock signal in different phases to the A/D converter unit, the method includes: a delay step which delays an output of each the A/D converter unit by a time corresponding to a cycle of the sampling clock signal; a multiplier step which multiplies outputs of the delay step by predetermined coefficients and which outputs the thus-multiplied signals; a totalizer step which outputs the total of outputs provided from the multiplier step; and an alternate output step which outputs an output of the delay step and an output of the totalizer step in an alternate manner; the output of the delay step being spaced a predetermined time from a time point at which the output of the totalizer step takes a maximum value.
According to an embotiment of the present invention, a computer-readable medium has a program of instructions for execution by the computer to perform an input delay correcting process for an input delay correcting system for an A/D converter having a plurality of A/D converter unit for converting analog signal into digital signals in synchronism with a sampling clock signal; and a clock signal supply unit which supplies the sampling clock signal in different phases to the A/D converter unit. The input delay correcting process includes: a delay processing which delays an output of each the A/D converter unit by a time corresponding to a cycle of the sampling clock signal; a multiplier processing which multiplies outputs of the delay processing by predetermined coefficients and which outputs the thus-multiplied signals; a totalizer processing which outputs the total of outputs provided from the multiplier processing; and an alternate output processing which outputs an output of the delay processing and an output of the totalizer processing in an alternate manner; the output of the delay processing being spaced a predetermined time from a time point at which the output of the totalizer processing takes a maximum value.
REFERENCES:
patent: 5956371 (1999-09-01), Yamane
patent: 6384756 (2002-05-01), Tajiri et al.
Advantest Corporation
Jeanglaude Jean Bruner
Lowe Hauptman & Gilman & Berner LLP
Tokar Michael
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