Input circuit having improved noise immunity

Details Input circuit having improved noise immunity Input circuit having improved noise immunity

1988-07-21

1990-03-13

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307451, 307542, 307546, 307548, H03K 1716, H03B 104

Patent

active

049085280

ABSTRACT:
An improved CMOS input circuit is disclosed. A conventional CMOS input circuit having a plurality of inverter stages is used. The improvement comprises a N-type MOS transistor with the source connected to ground potential and the drain connected to the output node of one of the inverters. A capacitor couples a ground transient to the gate of the first N-type MOS transistor. An N-type MOS transistor provides AC isolation between the input node and the gate of the first N-type MOS transistor. A similar structure is shown for a P-type transistor connected to the power source.

REFERENCES:
patent: 4211942 (1980-07-01), Aoki et al.
patent: 4758749 (1988-07-01), Rapp
patent: 4763023 (1988-08-01), Spence

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