Input circuit for logic circuit having node and operating method

Details Input circuit for logic circuit having node and operating method Input circuit for logic circuit having node and operating method

1991-09-09

1992-05-05

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 307279, 307530, 307481, 3072964, H03K 19096, H03K 1716

Patent

active

051110784

ABSTRACT:
An address buffer circuit comprises a flip-flop circuit having first and second input nodes and connected between a power-supply potential and a ground potential. In addition, first, second and third transistors are connected in series in that order from the side of the ground between the first input node and the ground potential, to constitute a first input circuit, and fourth, fifth and sixth transistors are connected in series in that order from the side of the ground between the second input node and the ground potential, to constitute a second input circuit. An external address signal is applied to a control terminal of the first transistor, and a reference potential is applied to a control terminal of the fourth transistor. At the time of operating the address buffer circuit, the second and fifth transistors are first turned on, to bring the first and second input circuits into the operating state and then, to bring the flip-flop circuit into the operating state. Thereafter, the third and sixth transistors are turned off, to bring the first and second input circuits into the non-operating state.

REFERENCES:
patent: 4149099 (1979-04-01), Nagami
patent: 4195239 (1980-03-01), Suzuki
patent: 4561702 (1985-12-01), McAdams
patent: 4733112 (1988-03-01), Yamaguchi

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