Television – Camera – system and detail – Unitary image formed by compiling sub-areas of same scene
Reexamination Certificate
1997-10-20
2001-10-23
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Unitary image formed by compiling sub-areas of same scene
C348S231900
Reexamination Certificate
active
06307587
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to an input circuit for an image processor.
When processing images that vary both spatially and in time, the most challenging task typically is to process the varied information in a manner that provides a good, valid solution in real-time. Because software-based approaches typically are slower than hardware approaches, hardware is often chosen to process the images.
One type of hardware that is used to process images is an analog image processor (e.g., a Three Dimensional Artificial Neural Network (3DANN)). The image processor typically relies on input from an imager which electrically captures the image and presents an electrical representation of the image to the image processor. The image processor has a limit on the size of image that the processor can process at one time. As a result, typically, the size of the imager is chosen so that the size limit of the image processor is not exceeded.
SUMMARY OF INVENTION
In general, in one aspect, the invention features a circuit that is used with an imager that is capable of capturing an image. The circuit includes a memory that is configured to during a first time interval, store a first representation of a first subimage of the image from the imager and during a second time interval, receive an update from the imager and use the update and the first representation to store a second representation of a second subimage of the image. The first subimage partially overlaps the second subimage, and the update represents a portion of the second subimage that is not present in the first subimage. The circuit also has an output circuit that is configured to during the first time interval, use the first representation to generate output signals representative of the first subimage and during the second time interval, use the second representation to generate output signals representative of the second subimage.
The advantages of the invention may include one or more of the following. Any type and size of imager can be interfaced to an image processor. The image processor can process images in a piecewise fashion. Data transfer times from the imager to the processor are reduced. Power consumption is minimized. The circuit has a compact size.
Implementations of the invention may include one or more of the following. The memory may include memory cells that are configured to shift the first representation among the cells to form the second representation. The memory cells may be configured to discard a portion of the first representation to form the second representation.
The memory cells may include first, second and third groups of memory cells that are configured to store the first representation during the first time interval. The first group of memory cells may be configured to receive the update during the second time interval, and the second group of memory cells may be configured to discard a portion of the first representation during the second time interval. The portion may be equivalent in size to the update. The third group of memory cells may be configured to shift the first representation from the first group of memory cells toward the second group of memory cells during the second time interval.
The second subimage may be offset from the first subimage along one of at least two different directions, and during the second time interval, the memory cells may be also configured to shift the first representation among the cells along the one of the directions. The memory may also include at least two shift register banks. Each different shift register bank may be associated with a different one of the directions. Each bank may be configured to receive the update when the direction associated with the bank corresponds to the one of the directions.
The second subimage may be offset from the first subimage along one of at least three different directions, and during the second time interval, the memory cells may be further configured to shift the first representation among the cells along the one of the directions. The memory may also include at least three shift register banks. Each different shift register bank may be associated with a different one of the directions. Each bank may be configured to receive the update when the direction associated with the bank corresponds to the one of the directions. At least two of the directions may be orthogonal to each other, and at least two of the directions may be directly opposed.
The imager may include a rectangular array of pixel cells that are configured to capture the image. The array may be arranged in rows and columns, and each pixel cell may provide an output. The first representation may be indicative of the outputs of the pixel cells from a subregion (e.g., another rectangular array of pixel cells) of the array.
The update may be indicative of the outputs of the pixel cells from one of the rows or columns of the array. The output circuit may include digital-to-analog converters. Each different digital-to-analog converter may be connected to a different one of the memory cells.
In general, in another aspect, the invention features a method of processing an image. The method includes storing a first representation of a first subimage of the image. The first subimage is less than the whole image. During a first time interval, output signals representative of the first subimage are generated. During a second time interval, an update representing an additional portion of the image is received. The update and the first representation are used to store a second representation of a second subimage of the image. The first subimage partially overlaps the second subimage, and the update represents a portion of the second subimage not present in the first subimage. The method also includes using the second representation to generate output signals representative of the second subimage.
In general, in another aspect, the invention features a circuit for loading a second subimage of an image that is captured by an imager. The second subimage partially overlaps a first subimage of the image and is partially offset from the first subimage along one of at least two directions. The imager is capable of furnishing a first representation of the first subimage and an update representing a portion of the second subimage not present in the first subimage. The circuit includes at least two shift register banks, and each different shift register bank is associated with a different one of the directions and is configured to receive the update when the second subimage is offset from the first subimage along the direction.
The circuit includes memory cells that are connected to the banks and configured to during a first time interval, store the first representation in first, second and third groups of the memory cells. During the second time interval, a portion of the first representation stored in the second group of memory cells is discarded, the third group of memory cells shifts the first representation from the first group of memory cells toward the second group of memory cells, and the first group of memory cells stores the update. The circuit also has analog-to-digital converters, and each different analog-to-digital converter is connected to a different one of the memory cells. The converters are configured to during the first time interval, generate output signals representative of the first representation, and during the second time interval, generate output signals representative of the second representation.
Other advantages and features will become apparent from the following description and from the claims.
REFERENCES:
patent: 5208583 (1993-05-01), Cusick et al.
patent: 5510830 (1996-04-01), Ohia et al.
patent: 5528290 (1996-06-01), Saund
patent: 5706362 (1998-01-01), Yabe
patent: 5880778 (1999-03-01), Akagi
California Institute of Technology
Fish & Richardson P.C.
Garber Wendy R.
Nguyen Luong
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