Pulse or digital communications – Synchronizers – Feedback – receiver to transmitter
Reexamination Certificate
2006-12-12
2006-12-12
Kim, Kevin (Department: 2611)
Pulse or digital communications
Synchronizers
Feedback, receiver to transmitter
C375S371000
Reexamination Certificate
active
07149267
ABSTRACT:
An input circuit includes: a comparator; first and second delay circuits; a selector; an input buffer; and a holding circuit. The comparator compares the leading and/or trailing edges of a data signal, supplied from the input buffer, to an edge of a clock signal on which the data signal is intended to be latched. Based on the results of the comparison, the first and second delay circuits delay the clock signal for respectively predetermined amounts of time. If the data signal is logically high, then the selector selects a delayed clock signal supplied from the first delay circuit. Alternatively, if the data signal is logically low, then the selector selects another delayed clock signal supplied from the second delay circuit. Then, the delayed clock signal, selected by the selector, is latched in the holding circuit. The input circuit with such a configuration prevents skewing from being caused by a difference in length between the transition interval of the data signal from H into L level and that of the data signal from L into H level. As a result, data can be transferred at a much higher speed even if the clock frequency is very high.
REFERENCES:
patent: 4819251 (1989-04-01), Nelson
patent: 5636165 (1997-06-01), Amatangelo et al.
patent: 5663914 (1997-09-01), Kwon
patent: 5712884 (1998-01-01), Jeong
patent: 5732027 (1998-03-01), Arcoleo et al.
patent: 5952857 (1999-09-01), Suzuki
patent: 5963606 (1999-10-01), Drost et al.
patent: 6157229 (2000-12-01), Yoshikawa
patent: 6178212 (2001-01-01), Akashi
patent: 6275547 (2001-08-01), Saeki
patent: 0884732 (1998-06-01), None
patent: 2316208 (1998-02-01), None
patent: 63-9220 (1988-01-01), None
patent: 05-14167 (1993-01-01), None
patent: 05-83111 (1993-04-01), None
patent: 05-110550 (1993-04-01), None
patent: 07-86900 (1995-03-01), None
patent: 07131311 (1995-05-01), None
patent: 08-194664 (1996-07-01), None
patent: 08-237101 (1996-09-01), None
patent: 09-162706 (1997-06-01), None
Terada Yutaka
Yoshikawa Takefumi
No associations
LandOfFree
Input circuit and output circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Input circuit and output circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input circuit and output circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3694287