Input circuit and output circuit

Details Input circuit and output circuit Input circuit and output circuit

2001-06-21

2002-07-23

Nguyen, Matthew (Department: 2838)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S427000

Reexamination Certificate

active

06424206

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device which has an internal voltage reduction circuit for providing an internal voltage by reducing an external voltage.
2. Description of the Related Art
Recently, the degree of integration of semiconductor integrated circuits has increased. MOS transistors have become smaller in order to provide many functions in one chip.
The accuracy of processing machines has also improved, and therefore the size of MOS transistors can be easily reduced.
However, as the MOS transistors become smaller, a source voltage for circuits which comprise semiconductor integrated circuits, that is, the voltage of an external power source supplied to the internal circuit of the semiconductor integrated circuit, may be more likely to deteriorate the internal MOS transistors.
Although the size of the MOS transistor is being reduced, the operating voltage of the MOS transistors has not changed (it has is not been reduced). Therefore, the voltage can exceed the withstand voltage of the MOS transistors, reducing the reliability.
The operating voltage of the MOS transistor is set according to standards (or working conditions) independently from the reduced size of the MOS transistors. Since the size of MOS transistors is being reduced, the standards for semiconductor integrated circuits using the MOS transistors should be revised. However, the operating voltage according to the standards have not been reduced.
Therefore, as shown in
FIG. 9
, an internal voltage reduction circuit
100
provided in the semiconductor integrated circuit reduces the voltage VEX (for example, 3.3 V) from an external power source to an internal voltage VINT (for example, 2.0 V) which meets the withstand voltage of the reduced MOS transistors, and supplies the internal voltage to the internal circuit
101
.
Thus, the electric power consumption can be reduced in the operation of the semiconductor integrated circuit.
However, the input circuit
102
and the output circuit
103
must be capable of withstanding the voltage VEX from the external power source.
That is, in a p-channel MOS transistor
104
in the input circuit
102
, when the voltage of an input signal IN is at the H level, the withstand voltage between a drain with a substrate and a gate is exceeded. When the voltage of the input signal IN is at the L level, the withstand voltage between a source and the gate is exceeded.
In an n-channel MOS transistor in the input circuit
102
, when the voltage of the input signal IN is at the H level, the withstand voltage between the source and the gate is exceeded, and when the voltage of the input signal IN is at the L level, the withstand voltage between the drain with a substrate and the gate is exceeded.
Similarly, in a p-channel MOS transistor
106
in the output circuit
103
, when a signal INO is at the H level, the withstand voltage between the source and the gate is exceeded, and when the signal INO is at the L level, the withstand voltage between the drain with a substrate and the gate is exceeded.
In an n-channel MOS transistor
107
in the input circuit
103
, when the signal INO is at the H level, the withstand voltage between a source and a gate is exceeded, and when the signal INO is at the L level, the withstand voltage between a drain with a substrate and a gate is exceeded. The voltage of the signal INO at the H level is changed from the internal voltage VINT to the external voltage VEX by a level shift circuit
108
.
Thus, the input circuit
102
and the output circuit
103
must be capable of the voltage VEX of the external power source to send and receive signals to and from an external circuit.
Therefore, for the MOS transistor to have a gate which withstands the voltage VEX of the external power source, the oxide film of the gate of the MOS transistor must have a thickness which allows it to withstand the voltage VEX of the external power source.
According to the above structure, the semiconductor integrated circuit has input circuit
102
and output circuit
103
with gates which can withstand the voltage of the external power source.
However, the process for manufacturing the semiconductor integrated circuit must produce two kinds of MOS transistors. One of the MOS transistors has a thin gate oxide film (with a thickness of 4 nm), while the other MOS transistor has a thick gate oxide film (with a thickness of 9 nm).
Because two kinds of gate oxide films with different thicknesses must be produced, at least four extra steps are required as compared with the normal manufacturing process for producing gate oxide films with the same thickness. Therefore, the manufacturing costs are increased, and the price of the produced chip is also disadvantageously increased.
To solve this problem, a circuit structure in which the gate oxide films in the MOS transistors which constitute the input circuit and the output circuit and the gate oxide films in the MOS transistors which constitute the internal circuit have the same thickness has been proposed.
In the input circuit shown in
FIG. 10
, the voltage reduction circuit
115
reduces the external voltage VEX to the internal voltage VINT, and supplies the voltage VINT to the internal circuit. When the voltage of the input signal IN is at the L level, the voltage of a source and a gate of a p-channel MOS transistor
110
is within the withstand voltage. Thus, the withstand voltage is satisfied.
Because a p-channel transistor
112
whose gate is connected to ground is inserted between a MOS transistor
110
and an n-channel MOS transistor
113
, the voltage at the drain of the MOS transistor
110
is reduced. When the voltage of the input signal IN is at the H level, the voltage between the drain and the gate of the MOS transistor
110
is within the withstand voltage. Thus, the withstand voltage is satisfied.
The phrase “the voltage is within the withstand voltage (satisfy the withstand voltage)” means that a voltage less than the withstand voltage of the gate oxide film of the MOS transistor is applied between a gate and a source (or a drain).
Similarly, an n-channel MOS transistor
114
is inserted between a gate of an n-channel MOS transistor
113
and an input terminal
116
(which is connected to an external pad).
When the input signal IN is at the H level, the voltage of the signal at the H level (the voltage VEX of the external power source) applied to the gate of the MOS transistor
113
is reduced to VEX−VTN by a threshold voltage VTN of a MOS transistor
114
so that the voltage between the gate and the source of the MOS transistor
113
is within the withstand voltage.
When the input signal IN is at the L level, the voltage of the signal at the L level (the ground level) applied to the gate of the MOS transistor
113
is increased to VTP by the threshold voltage VTP of the MOS transistor
114
, and the voltage applied to the drain is changed to the internal voltage VINT by a voltage reduction circuit
115
. Thus, the withstand voltage of the gate and the drain of the MOS transistor
113
is satisfied.
In the output circuit shown in
FIG. 11
, a p-channel MOS transistor
120
, a p-channel MOS transistor
121
, an n-channel transistor
122
, and an n-channel MOS transistor
123
are connected in series.
The source of the MOS transistor
120
is connected to a terminal at an external voltage VEX. The signal SB output from the level shifter
125
is input to the gate of the MOS transistor
120
. The drain of the MOS transistor
120
is connected to a source of the MOS transistor
121
.
The control signal SP at a voltage VSP is continuously input from the reference power source
126
to the gate of the MOS transistor
121
. the control signal SN at a voltage VSN is continuously input from the reference power source
126
to the gate of the MOS transistor
122
.
When the MOS transistor
120
is turned on, the voltage VSP of the control signal SP sets the voltage between the gate and the source (or the drain) of the MOS transistor
121
to less than the withs

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