Input circuit

Details Input circuit Input circuit

2000-08-24

2001-08-14

Patel, Rajankani B. (Department: 2838)

Electric power conversion systems

Current conversion

With means to introduce or eliminate frequency components

C327S068000, C327S079000

Reexamination Certificate

active

06275394

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input circuit and, more particularly, to an input circuit of the class which processes a given input signal to remove the noise components contained therein and to regulate the voltage level thereof, and then supplies the processed as an output signal of the input circuit to a subsequent semiconductor integrated circuit.
2. Prior Art
As indicated in
FIG. 5
, a prior art input circuit
1
for use in a semiconductor integrated circuit is made up of a Schmitt buffer
11
, a pull-down resistance
13
, and an N-channel type transistor (referred to as just “N-transistor” hereinafter)
15
.
The Schmitt buffer
11
is such a buffer that has two threshold levels i.e. an upper threshold level and a lower one and varies the level of its output signal OUT depending on whether the voltage of an input signal IN exceeds the above two threshold levels, that is, whether the voltage of the input signal IN is higher than the upper threshold level or lower than the lower the threshold level. When the voltage of the input signal IN is lower than the lower threshold level, the corresponding output signal OUT is made to be a logical low level (referred to as “L-level” hereinafter), and when the voltage of the input signal IN which is higher than the upper threshold level, the corresponding output signal OUT is made to be a logical high level (referred to as “H-level” hereinafter). In the following, the above prior art input circuit will be discussed assuming that the input signal IN inputted to the first node N
1
is either at the H-level or in the high impedance state (referred to as “HiZ” hereinafter).
The Schmitt buffer
11
is made up of 4 P-channel type transistors (referred to as just “P-transistor” hereinafter)
11
-
1
,
11
-
3
,
11
-
5
and
11
-
7
, and 4 N-transistors
11
-
2
,
11
-
4
,
11
-
6
and
11
-
8
.
Each gate of the P-transistor
11
-
1
and the N-transistor
11
-
2
is commonly connected with the first node N
1
to which the input signal IN is externally inputted, and each drain of them is commonly connected with the second node N
2
. The source of the P-transistor
11
-
1
is connected with a power source VDD, and the source of the N-transistor
11
-
2
is connected with the ground GND.
Each gate of the P-transistor
11
-
3
and the N-transistor
11
-
4
is commonly connected with the third node N
3
from which the output signal OUT is put out, and each drain of them is commonly connected with the second node N
2
. The source of the P-transistor
11
-
3
is connected with the drain of the P-transistor
11
-
5
, and the source of the N-transistor
11
-
4
is connected with the drain of the N-transistor
11
-
6
.
Each gate of the P-transistor
11
-
5
and the N-transistor
11
-
6
is commonly connected with the first node Ni. The source of the P-transistor
11
-
5
is connected with a power source VDD, and the source of the N-transistor
11
-
6
is connected with the ground GND.
Each gate of the P-transistor
11
-
7
and the N-transistor
11
-
8
is commonly connected with the second node N
2
, and each drain of them is commonly connected with the third node N
3
. The source of the P-transistor
11
-
7
is connected with a power source VDD, and the source of the N-transistor
11
-
8
is connected with the ground GND.
One end of the pull-down resistance
13
is connected with the ground GND, and the other end thereof is connected with the source of an N-transistor
15
. The drain of the N-transistor
15
is connected with the first node N
1
. The N-transistor
15
is controlled to be turned on or off by means of a pull-down selection signal PUDN inputted to the gate thereof.
When the pull-down resistance selection signal PUDN of the H-level is inputted to the prior art input circuit
1
as made up like the above, the N-transistor
15
is turned on, so that the first node N
1
is pulled down to the potential of the ground GND by the N-transistor
15
and the pull-down resistance
13
. Contrary to this, when the pull-down resistance selection signal PUDN of the L-level is inputted, the N-transistor
15
is turned off, so that the first node N
1
is electrically separated from the ground GND.
By the way, according to the prior art input circuit
1
, however, when the pull-down resistance selection signal is at the H-level, if the H-level input signal IN is inputted to the first node N
1
, the current I
1
is caused to flow through the N-transistor
15
and the pull-down resistance
13
as well. It is needed, therefore, to minimize such current I
1
in order to achieve the reduction of electric power consumption in the input circuit
1
.
Then, for meeting this need, it might be considered to electrically separate the first node N
1
from the ground GND, thereby preventing the current I
1
from flowing through the N-transistor
15
and the pull-down resistance
13
. More specifically, for a period of time during which there is no need for the input circuit
1
to generate any output signal OUT in response to the input signal IN, in other words, a subsequent circuit of the input circuit
1
does not require any output signal OUT received thereby, if the pull-down resistance selection signal PUDN be the L-level and the N-transistor
15
be in the OFF state, the first node N
1
can be electrically separated from the ground GND. With this, the current I
1
can be prevented from flowing through the N-transistor
15
and the pull-down resistance
13
even if the input signal IN is at the H-level.
If, however, the input signal IN gets in the HiZ state in the condition that the first node N
1
is electrically separated from the ground GND, the first node Ni will become an unstable intermediate level, which is neither the H-level nor the L-level. In this state, both of the P-transistor
11
-
1
and the N-transistor
11
-
2
equipped in the Schmitt buffer
11
will fall into the incomplete state i.e. neither ON nor OFF state, and there will be generated a so-called penetration current I
2
flowing between the source of the P-transistor
11
-
1
and the drain of the N-transistor
11
-
2
. This penetration current I
2
is also against the reduction of electric power consumption in the input circuit
1
.
The invention has been made in view of such problems as described above, and its main object is to provide an input circuit with smaller electric power consumption.
SUMMARY OF THE INVENTION
In order to solve the problems as described above, according to the invention, there is provided an input circuit which generates an output signal at an output node in response to an input signal received at an input node, and supplies the output signal to an internal circuit in accordance with an input/output control signal of the enable state. This input circuit is characterized by that it is made up of: a first voltage level production section which has an input terminal, an output terminal, a first power source terminal, and a second power source terminal, produces a first voltage level, in response to the voltage level of the input node, based on a voltage level applied to the first power source terminal and a voltage level applied to the second power source terminal as well, and supplies the first voltage level to an intermediate node; a second voltage level production section which produces a second voltage level in response to the voltage level of the intermediate node, and supplies the second voltage level to the output node; a voltage level comparison section which detects whether or not the voltage level of the output node coincides with the voltage level of the input/output control signal, and outputs a detection signal in correspondence with a detection result; a voltage level holding section which holds a voltage level of the output node given at the time when said input/output control signal changes the state thereof from the enable state to the disable state; and a power source terminal selection section which makes either the first or second power source terminal of the first voltage level production

Affiliated with

Also associated with

Rating

Input circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Input circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2533335