Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-05-19
2001-08-21
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C326S104000
Reexamination Certificate
active
06278319
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89109104, filed May 12, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an input-buffering device. More particularly, the present invention relates to the design of an adjustable voltage divider capable of generating a bias signal for controlling the first stage input buffering device of a NOR gate so that reversal of output signal difference at different times caused by trigger point shift is prevented.
2. Description of Related Art
Most conventional input buffering devices use a simple NOR gate structure to serve as a first stage input for transforming a transistor-transistor logic (TTL) signal into a CMOS standard sign.
FIG. 1
is a circuit diagram of a conventional input-buffering device. As shown in
FIG. 1
, the circuit includes two PMOS transistors
10
and
12
, two NMOS transistors
14
and
16
and five inverters
18
,
20
,
22
,
24
and
26
.
The source terminal of the PMOS transistor
10
is connected to a high voltage Vdd and the gate terminal is connected to a first input signal CECTL (Chip Enable Control). In addition, the source terminal of the PMOS transistor
12
is connected to the drain terminal of the PMOS transistor
10
and the gate terminal is connected to a second input signal AX. The drain terminal of the NMOS transistor
14
is connected to the drain terminal of the PMOS transistor
12
. The gate terminal of the NMOS transistor
14
is connected to the second input signal AX while the source terminal is connected to a low voltage Vss. The drain terminal of the NMOS transistor
16
is connected to the drain terminal of the PMOS transistor
12
. The gate terminal of the NMOS transistor
16
is connected to the first input signal CECTL while the source terminal of the NMOS transistor
16
is connected to the low voltage Vss.
The input terminal of the inverter
18
is connected to the drain terminal of the PMOS transistor
12
. The input terminal of the inverter
20
is connected to the output terminal of the inverter
18
, and the output terminal of the inverter
20
is connected to the drain terminal of the PMOS transistor
12
. The input terminal of the inverter
22
is connected to the output terminal of the inverter
18
, and the output terminal of the inverter
22
is connected to a first output signal X
B
. The input terminal of the inverter
24
is connected to the output terminal of the inverter
18
. The input terminal of the inverter
26
is connected to the output terminal of the inverter
24
, and the output terminal of the inverter
26
is connected to a second output signal X.
The trigger point of the input buffering device shown in
FIG. 1
is largely determined by the dimensions of the serially connected PMOS pull-up devices (that is, PMOS transistors
10
and
12
) and the parallel-connected NMOS pull-down devices (that is, NMOS transistors
14
and
16
). However, different ranges of source voltage Vcc (such as 4.5-5.5V, 2.7-3.6V and 1.8-2.2V) are often required due to market forces. If related products are used with a conventional input buffering device and identical signal magnitudes are input, a trigger point shift may occur due to a different in source voltage. Hence, high-to-low or low-to-high transmission of input TTL signal may be affected, leading to reversal of output signal difference at different times produced by the NOR gate output terminal. Hence, a fast and a slow transmission will result. Such a fluctuation in transmission speed under different range of source voltage often produces different reverse speed signal that may affect access time of high-speed product (such as synchronous SRAM).
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide an input-buffering device capable of resolving trigger point shift problem resulting from source voltage fluctuation. An adjustable voltage divider circuit is used to control a first stage input buffer. Consequently, a rise in source voltage will only result in a small magnitude variation of the trigger point. Hence, no matter if the input signal transits from a low to-high or a high-to-low level, timing of the reverse signal produced by the input buffer at the output terminal is uniform. Since transmission rate is uniform, an imbalance in input signal transmission due to source voltage variation is reduced. Ultimately, data access timing of the electronic device is in an optimally balanced state.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an input-buffering device. The device includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, at least one group transistor assembly and an adjustable voltage divider circuit. The source terminal of the first PMOS transistor is connected to a high voltage. The gate terminal of the first PMOS transistor receives a first input signal. The source terminal of the second PMOS transistor is connected to the drain terminal of the first PMOS transistor. The gate terminal of the second PMOS transistor receives a second input signal. The drain terminal of the first NMOS transistor is connected to the drain terminal of the second PMOS transistor. The gate terminal of the first NMOS transistor receives the second input signal. The source terminal of the first NMOS transistor is connected to a low voltage. The drain terminal of the second NMOS transistor is connected to the drain terminal of the second PMOS transistor. The gate terminal of the second NMOS transistor receives the first input signal. The source terminal of the second NMOS transistor is connected to the low voltage.
The input terminal of the first inverter is connected to the drain terminal of the second PMOS transistor. The input terminal of the second inverter is connected to the output terminal of the first inverter and the output terminal of the second inverter is connected to the drain terminal of the second PMOS transistor. The input terminal of the third inverter is connected to the output terminal of the first inverter. The output terminal of the third inverter outputs a first output signal. The input terminal of the fourth inverter is connected to the output terminal of the first inverter. The input terminal of the fifth inverter is connected to the output terminal of the fourth inverter. The output terminal of the fifth inverter outputs a second output signal.
Each transistor assembly includes a first control NMOS transistor and a second control NMOS transistor. The drain terminal of the first control NMOS transistor is connected to the drain terminal of the second PMOS transistor. The gate terminal of the first control NMOS transistor receives the second input signal. The drain terminal of the second control NMOS transistor is connected to the source terminal of the first control NMOS transistor. The source terminal of the second control NMOS transistor is connected to the low voltage. The adjustable voltage divider circuit generates a bias voltage signal and transmits the same to the gate terminal of the second control NMOS transistor.
The adjustable voltage divider circuit includes a pull-up circuit for controlling the value of a threshold voltage and a variable resistor connected to the pull-up circuit for generating a bias voltage signal. The pull-up circuit includes at least one pull-up PMOS transistor and a control PMOS transistor. The source terminal of the pull-up PMOS transistor is connected to a high voltage and the gate terminal of the pull-up PMOS transistor is connected to its drain terminal. The source terminal of the control PMOS transistor is connected to the drain terminal of the pull-up PMOS transistor and the gate terminal of the control PMOS transistor is connected to the low voltage. The drain terminal of the control
Lam Tuan T.
Nguyen Linh
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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