Input buffer with hysteresis characteristics

Details Input buffer with hysteresis characteristics Input buffer with hysteresis characteristics

1992-12-21

1994-09-20

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307359, H03K 1716

Patent

active

053492463

ABSTRACT:
An input buffer circuit is disclosed which has feedback hysteresis transistors having similar size characteristics as the drive transistors. The drive transistors are located in a first inverting CMOS stage, connected in conventional CMOS inverter fashion. The drains of the drive transistors are connected to the input of an inverter, the output of which drives the signal to elsewhere in the integrated circuit. A first hysteresis leg is provided, consisting of a plurality of p-channel transistors with their source/drain paths in series between the input of the inverter and a power supply voltage; the gate of at least one of the p-channel hysteresis transistors is coupled to the output of the inverter, and the gates of those of the hysteresis transistors that are not coupled to the inverter output are biased to ground. A second hysteresis leg of n-channel hysteresis transistors, similarly but complementarily configured, is provided between ground and the inverter input. The hysteresis transistors each have channel lengths substantially the same as the drive transistors, thus reducing the capacitive load at the output of the inverter and also ensuring good tracking over process variations; the channel widths of the hysteresis transistors may also be made sufficiently wide to avoid small width effects, and thus also provide improved tracking.

REFERENCES:
patent: 4490633 (1984-12-01), Noufer et al.
patent: 4506168 (1985-03-01), Uya
patent: 4539489 (1985-09-01), Vaughn
patent: 4904884 (1990-02-01), O'Shaughnessy
patent: 5177376 (1993-01-01), Wellnitz
Sedra, et al., Microelectronic Circuits (Holt, Rinehart & Winston, 1982), pp. 734-735.

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