Input buffer type packet switching equipment

Details Input buffer type packet switching equipment Input buffer type packet switching equipment

2007-11-06

2007-11-06

Nguyen, Steven (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C710S052000

Reexamination Certificate

active

09750688

ABSTRACT:
Input buffer type packet switching equipment, which can output cells to an external output line having a slower output line rate than a corresponding input line rate without having buffers in its output line sections, is provided. The input buffer type packet switching equipment provides M input line buffers that store cells inputted from M input lines temporarily in a state that one of the M input line buffers stores cells inputted from corresponding one of the M input lines, in this the M is an integer being 2 or more, an M×N crossbar type switch, which provides N output lines, for switching cells outputted from the M input line buffers based on a cross point on/off control signal, in this N is an integer being 2 or more. The input buffer type packet switching equipment further provides N output line sections, which are provided for each of the N output lines of the M×N crossbar type switch, for outputting cells applied switching at the M×N crossbar type switch to N external output lines, and an arbiter that outputs a connection permission signal to one of the M input line buffers based on connection request signals outputted from the M input line buffers, and also outputs the cross point on/off control signal to the M×N crossbar type switch, and outputs the connection permission signal at a designated slower timing interval than a normal timing interval to one input line buffer that outputs cells to an external output line whose output line rate is slower than a corresponding input line rate. With this, the timing interval outputting the cells from one of the M input line buffers to the M×N crossbar type switch is made to be wider than the normal timing interval, therefore buffers in the output line sections are not needed.

REFERENCES:
patent: 5267235 (1993-11-01), Thacker
patent: 5742606 (1998-04-01), Iliadis et al.
patent: 5996019 (1999-11-01), Hauser et al.
patent: 6072772 (2000-06-01), Charny et al.
patent: 6343066 (2002-01-01), Magill et al.
patent: 02-158243 (1990-06-01), None
patent: 05-14397 (1993-01-01), None
patent: 07-66806 (1995-03-01), None
patent: 7-245610 (1995-09-01), None
patent: 09-321768 (1997-12-01), None
patent: 10-135971 (1998-05-01), None
patent: 2000-13403 (2000-01-01), None
patent: 2001-024641 (2001-01-01), None
patent: WO99/40754 (1999-08-01), None
4. H. Kim et al., “A High-Speed ATM Switch Architecture Using Random Access Input Buffers and Multi-Cell-Time Arbitration”,IEEE, vol. 1, Nov. 3, 1997, pp. 536-540.

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