Input buffer system using low voltage transistors

Details Input buffer system using low voltage transistors Input buffer system using low voltage transistors

2002-08-28

2004-08-31

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S333000, C326S062000, C326S080000

Reexamination Certificate

active

06784717

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of semiconductors and more particularly to an input buffer system.
BACKGROUND OF THE INVENTION
Semiconductor processing techniques are constantly improving and as they improve the required power supply voltages are reduced. The best semiconductor processing techniques today only require power supply voltages of around 1.8 volts. These processing techniques create transistors commonly referred to as thin oxide transistors. Thin oxide transistors are faster than the relatively thicker oxide transistors and can be used to produce denser circuits. Unfortunately, thin oxide circuits commonly have to interface with older technology circuits that have relatively high voltage power supplies (e.g., 2.5V, 3.0V or 3.3V). These relatively high voltage circuits contain the transistors commonly referred to as thick oxide transistors. When it is necessary that a signal be transmitted from a high voltage thick oxide circuit to a low voltage, thin oxide circuit, a buffer circuit is required to convert the signal from a high voltage to a lower voltage. Prior art solutions use a buffer circuit that has both thick oxide transistors (components) and thin oxide transistors (components). As a result, the processing of these circuits is relatively complex and expensive. Creating a buffer circuit with transistors that are all the thin oxide type is difficult since the gate oxide voltage stress limit of the thin oxide transistors is lower than the high voltages being applied from an external source. Another problem is creating an input buffer circuit with thin oxide transistors that does not consume current when the input is not transitioning.
Thus there exists a need for an input buffer system that overcomes the problems of the prior art circuits.
SUMMARY OF INVENTION
An input buffer system that overcomes these and other problems has an input clipping circuit. The input clipping circuit has a high voltage input and uses only thin oxide transistors. A high voltage detect circuit is coupled to the input clipping circuit. An input buffer circuit is coupled to the input clipping circuit and has a low voltage output. In one embodiment, the input buffer circuit is formed with transistors having only thin oxide. In another embodiment, the input clipping circuit has a gate bias circuit. In one embodiment, the gate bias circuit is coupled to a gate of a pass transistor.
In one embodiment, the input clipping circuit does not draw any supply current when the high voltage supply is within a normal operating range. In another embodiment, the input buffer circuit does not draw any supply current when it is in a standby mode.
In one embodiment, an input clipping circuit has a pass transistor with a drain coupled to an input signal. A gate bias circuit is coupled to a gate of the pass transistor. A high voltage detect circuit is coupled to the gate bias circuit. In one embodiment, the gate bias circuit has transistors that are only thin oxide transistors. In another embodiment, the input signal is a high voltage signal.
In one embodiment, the gate bias circuit includes a load element coupled to a high voltage power supply and a first controllable switch coupled between the load element and the gate of the pass transistor. In another embodiment, the gate bias circuit has a p-channel transistor with a gate coupled to the source of the pass transistor and has a drain coupled through a second controllable switch to a ground.
In one embodiment, the gate bias circuit has a bias input. In another embodiment, the bias input is coupled to the gate of the pass transistor through a controllable bias switch.
In one embodiment, a buffer circuit has a raised ground inverter coupled to an input. A low level restoring circuit is coupled to the raised ground inverter. A standard inverter is coupled to the low level restoring circuit. In one embodiment, the raised ground inverter includes a load element coupled to a ground. In another embodiment, the raised ground inverter includes transistors that are only thin oxide transistors.
In one embodiment, the low level restoring circuit has a pull down transistor with a gate coupled to the input and a source coupled to a ground. The drain of the pull down transistor is coupled to the standard inverter. In another embodiment, the low level restoring circuit has a n-channel transistor with a gate coupled to an output of the raised ground inverter and a drain coupled to a low voltage power supply. In another embodiment, the low level restoring circuit has a p-channel transistor coupled between the n-channel transistor and the standard inverter. In one embodiment, the n-channel transistor is a low threshold device.


REFERENCES:
patent: 4277782 (1981-07-01), Chao
patent: 5300832 (1994-04-01), Rogers
patent: 5333093 (1994-07-01), Krautschneider et al.
patent: 6069515 (2000-05-01), Singh
patent: 6282146 (2001-08-01), Guo et al.

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