Input buffer structure with single gate oxide

Details Input buffer structure with single gate oxide Input buffer structure with single gate oxide

2007-02-06

2007-02-06

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S206000, C326S081000

Reexamination Certificate

active

10859726

ABSTRACT:
An input buffer for interfacing a high voltage signal received at an input node to a low voltage circuit comprising low voltage devices is provided. The buffer includes a threshold adjustment circuit including an inverter coupled to a threshold adjusted output node. The inverter includes low voltage devices and is coupled between a high supply voltage node and a ground node. The inverter includes a first and second transistors having biasing nodes coupled to a low voltage supply node of the low voltage circuit and coupled to the threshold adjusted output node. The adjustment circuit provides at the threshold adjusted output node an inverted signal corresponding to the high voltage input signal. The buffer also includes a level shifting circuit including low voltage devices and provides a low voltage signal corresponding to the high voltage input signal in response to said inverted signal.

REFERENCES:
patent: 5917339 (1999-06-01), Kim
patent: 6288599 (2001-09-01), Coddington
patent: 6346829 (2002-02-01), Coddington
patent: 6683486 (2004-01-01), Hanson et al.
patent: 6690222 (2004-02-01), Nair
patent: 2001/0002797 (2001-06-01), Nebel
patent: 2004/0104756 (2004-06-01), Payne
Wang et al., “Level Shifters for High-Speed 1-V to 3.3-V Interfaces in a 0.13 um Cu-Interconnection/Low-k CMOS Technology”, 2001 IEEE, pp. 307-310.

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