Input buffer regenerative latch for ECL levels

Details Input buffer regenerative latch for ECL levels Input buffer regenerative latch for ECL levels

1990-04-02

1992-04-07

Nelms, David C.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307455, H03K 19092, H03K 19094

Patent

active

051031213

ABSTRACT:
An imput buffer regenerative latch circuit useful in BiCMOS integrated circuits is presented. The ECL input signal terminal is connected to the base of a bipolar transistor. The emitter of the transistor is connected to one of two input/out nodes of a CMOS regenerative latch circuit by the source/drain path of a MOS transistor. The second input/output node is similar connected to the emitter of a second bipolar transistor by the source/drain path of a second MOS transistor. The base of the second bipolar transistor is held at a reference voltage midway in the ECL voltage range. Latching occurs very quickly when the CMOS latch is activated.

REFERENCES:
patent: 4724343 (1988-02-01), Le Roux et al.
patent: 4806799 (1989-02-01), Pelley, III et al.
patent: 4864159 (1989-09-01), Cornelissen

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