Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1999-09-22
2001-02-20
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S112000
Reexamination Certificate
active
06191636
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a level shifter generally and, more particularly, to an input buffer/level shifter.
BACKGROUND OF THE INVENTION
The trend in modern central processing units (CPUs) and microprocessors is to reduce the power supply operating voltage in order to reduce power consumption and increase the chip density. The power supply reduction may impact other performance considerations as well. Due to the design considerations, memory devices, such as dynamic random access memories (DRAMs), may operate at a different supply voltage than the CPU. Some devices also may be required to use more than one power supply voltage so they can signal a CPU related device at one voltage and other devices at another voltage. The signals are generally generated by one circuit and are received by another circuit.
One such configuration occurs with modern microprocessors that operate with a nominal power supply voltages of about 2.5V, 1.8V, or lower, while other circuits in the computer operate with a power supply voltage of about 3.3V. To facilitate communication between devices operating at different voltages, an input buffer/level shifter circuit is used.
Referring to
FIG. 1
, a circuit diagram illustrates a conventional level shifter
10
. The level shifter
10
generates an output signal LSOUT in response to an input signal TTLIN. The level shifter
10
has a stage
12
and a stage
14
. The stage
12
is a CMOS inverter powered by the I/O power supply VCCIO. The stage
14
is a CMOS inverter powered by the core supply VPWR. The signal TTLIN swings between ground and VCCIO. The stage
12
inverts the signal TTLIN and presents the inverted signal to the stage
14
. The swing of the output of
12
is between ground and VCCIO. The stage
14
inverts the signal received from the stage
12
and presents the signal LSOUT at an output. The signal LSOUT swings between ground and VPWR.
Referring to
FIG. 2
, a circuit diagram illustrates another conventional level shifter
10
′. The circuit
10
′ has two stages
12
′ and
14
′. The stage
12
′ consists of a differential amplifier
18
and a voltage reference generator (VRG)
16
. The VRG
16
is connected to the positive input
20
of the differential amplifier
18
. The VRG sets the trip point for the stage
12
′. The input signal TTLIN is presented at the negative input
22
. The differential amplifier
18
presents a signal indicative of the input level with respect to the VRG level. The stage
14
′ is a CMOS inverter powered by the core supply VPWR. The stage
14
′ inverts the signal received from the differential amplifier
18
and generates the signal LSOUT that swings between ground and VPWR.
With the increasing speeds and ever shrinking area that modern chips must work with, an input buffer/level shifter that operates faster, requires less space than the conventional designs, and uses no standby current for low power is desirable. The VRG
16
uses a current source, and requires standby current.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a first device and a second device. The first device may be configured to operate at a first supply voltage and may be configured to generate a pull-up signal in response to an input signal. The second device may be configured to operate at a second supply voltage that is lower than the first supply voltage. The second device may be configured to generate an output signal in response to (i) the input signal and (ii) the pull-up signal.
The objects, features and advantages of the present invention include providing a circuit that may (i) operate nearly twice as fast as a two stage CMOS inverter design, (ii) require no reference voltages, (iii) requires zero (or negligible) stand-by current (neglecting sub-threshold leakage), (iv) have a relatively small layout footprint, (v) provide a tighter Vih/Vil window across process and temperature corners, and/or (vi) provide an improved speed/power product.
REFERENCES:
patent: 4121203 (1978-10-01), Edwards et al.
patent: 4713600 (1987-12-01), Tsugaru et al.
patent: 5903142 (1999-05-01), Mann
patent: 6069515 (2000-05-01), Singh
patent: 6094083 (2000-07-01), Noda
patent: 6107857 (2000-08-01), Orisaka et al.
Cress Daniel Eric
Hunt Jeffery Scott
Nagarajan Muthu
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Miller Robert M.
Nu Ton My-Trang
LandOfFree
Input buffer/level shifter does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Input buffer/level shifter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input buffer/level shifter will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2589560