Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-06-28
2002-10-01
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S170000, C327S391000
Reexamination Certificate
active
06459307
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims priority from Korean Application, entitled “Input Buffer having Double Path ” Application No. 2000-36386 and filed on Jun. 29, 2000 and incorporates by reference its disclosure for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input buffer having dual paths in a semiconductor device, and, more particularly, to an input buffer capable of increasing input signal processing speed by using dual-path input buffers.
2. Prior Art of the Invention
Generally, a semiconductor device includes a terminal for receiving external input signals and a power voltage. A number of control signals are applied to the terminal, which in turn supplies the signals to an inner chip of the semiconductor device through an external pin of a package. An input buffer is indispensable for detecting control signals. In semiconductor devices that use CMOS logic, the external input signals must be adapted or converted to CMOS logic levels within the chip. Therefore, a CMOS semiconductor device must have at least one input buffer capable of converting signals from external levels to internal levels.
The input buffer used in a CMOS semiconductor device can have various forms. For this reason, the input buffer must be properly designed to correspond to the device. For example, in the art there is a static input buffer of the inverter type (i.e., CMOS inverter) which has both a PMOS device and an NMOS device. The input of the CMOS inverter is coupled to an external terminal and the output of the CMOS inverter is coupled to an internal signal transfer gate. The signals passing through the two buffers (e.g., the inverter and gate) are converted to a CMOS logic level commensurate with or equivalent to the internal signals having the full range of driving between a voltage (e.g., VDD) and a ground voltage.
Another example is a differential type input buffer in which one gate of a MOS pair (i.e., NMOS-PMOS pair) having a current-mirror-type current source is coupled to a reference voltage and the other gate is coupled to the input terminal. These two terminals are coupled to an input of a second buffer, which is a CMOS inverter having CMOS-level output.
The logic threshold voltage of the input buffer typically has a median value of logic input high VIH and logic input low VIL. Therefore, the logic high signal and the logic low signal are designed to transfer at the same speed.
The time needed to adapt or convert an external control signal to a CMOS logic level signal through an internal input buffer varies depending on conditions. For example, when the slew (V/sec) of an external control signal is great, the conversion time is short. If the logic high level (VIH) of an external signal is higher than the logic low level (VIL), the high signal is rapidly transferred. Conversely, if the logic high level of an external signal is lower than the logic low level, the low signal is rapidly transferred. Therefore, in order to balance the two logic signals, the slew of the external input signal and the flows of the VIH and the VIL must be constant.
FIG. 1
is a circuit diagram of a conventional input buffer. In a conventional input buffer, one input terminal is coupled to one input buffer. An internal operation signal processed by the input buffer is applied for internal operation of the semiconductor device. Since both the logic high signal and the logic low signal of the internal operation signal are transferred through the same buffer, transfer characteristics of the logic high signal and the logic low signal are designed to be equal. That is, the threshold voltage VIH+VIL/2 is applied and inversion is executed by variation of the input signal.
In the conventional input buffer, a first stage of the input buffer could be enlarged (i.e., increased device size) for faster transfer of the external control signal, but this results in increased power consumption. Although the size of the buffer input can be designed to skew its output for a special-purpose input buffer to effect a fast transfer of the logic high signal, this causes serious distortion of the other signal (i.e., logic low). That is, when the high signal is highlighted, or active, the low signal is distorted and, conversely, when the low signal is highlighted, or active, the high signal is distorted.
The conventional input buffer design thus has at least two disadvantages. First, when the external control signal input conditions change, the transfer speed of the internal signal cannot be increased without distorting either the logic high signal or the logic low signal. Second, input buffer enlargement to increase the transfer speed of the external control signal leads to increased power consumption. Therefore, there is a need to overcome these disadvantages.
SUMMARY OF THE INVENTION
The present invention provides a dual-path input buffer for increasing the input signal processing speed by using two input buffers, where each input's input characteristics differ from each other.
In accordance with one aspect of the present invention, an input buffer of a semiconductor device comprises: an input terminal receiving an external input signal; and a first and a second input buffer, both coupled to the input terminal for transferring the received external input signal, wherein the output signal of the second input buffer is blocked when the first input buffer transfers the received external input signal, and the output signal of the first input buffer is blocked when the second input buffer transfers the received external input signal.
In accordance with another aspect of the present invention, an input buffer of a semiconductor device comprises: an input terminal receiving an external input signal; and a first and a second input buffer, both coupled to the input terminal for transferring the received external input signal; a control signal generating circuit receiving the outputs of the first and second input buffers to generate a control signal for controlling the transfer paths of the first and second input buffers; and a latch circuit receiving signals from the first and second input buffers to generate an internal operation signal for the semiconductor device.
REFERENCES:
patent: 5414312 (1995-05-01), Wong
patent: 5699000 (1997-12-01), Ishikuri
patent: 5825215 (1998-10-01), Sugio et al.
patent: 5923192 (1999-07-01), Hasegawa
patent: 6304120 (2001-10-01), Taito
patent: 6307409 (2001-10-01), Wrathall
Hynix Semiconductor
Townsend and Townsend / and Crew LLP
Tran Toan
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