Input buffer for supplying semiconductor device with...

Details Input buffer for supplying semiconductor device with... Input buffer for supplying semiconductor device with...

1998-02-05

2001-02-06

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

Reexamination Certificate

active

06184738

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input buffer of a semiconductor device, and in particular, relates to an input buffer of a semiconductor device which compares an external reference potential with an external signal and supplies an internal signal to an internal circuit according to the result of the comparison.
2. Description of the Background Art
The recent increase in speed of the microprocessors accompanies the increase in the memory speed. Regarding data transmission between devices, a conventional interface of TTL (Transistor Transistor Logic) type has a limit on speed. Although the TTL type interface has no problem when the operating frequency is low, the overshoot and undershoot of an output signal becomes conspicuous when the operating frequency increases. Further, in the bus transmission system, irregularity of a signal due to reflection is a critical problem. Therefore, a high speed interface in which the amplitude of a signal is decreased is put into practical use.
FIG. 10
is a partially omitted circuit block diagram showing a structure of a semiconductor integrated circuit device (eg. DRAM) which employs an LVTTL (Low Voltage Transistor Transistor Logic) interface which is an interface of TTL type.
With reference to
FIG. 10
, this semiconductor integrated circuit device includes input buffers
81
.
1
-
81
.
m
, an internal circuit
82
and output buffers
83
.
1
-
83
.
n
. Input buffers
81
.
1
-
81
.
m
respectively receive external signals EXT
1
-EXTm, generate internal signals and supply them to internal circuit
82
. Internal circuit
82
carries out a prescribed operation (writing and reading operation of data in the case of DRAM) according to the internal signals supplied from input buffers
81
.
1
-
81
.
m
. Output buffers
83
.
1
-
83
.
n
amplify signals D
1
-Dn generated in internal circuit
82
and output them to the outside.
FIG. 11
is a circuit diagram illustrating a structure of the input buffer
81
.
m
shown in FIG.
10
.
Referring to
FIG. 11
, input buffer
81
.
m
includes P channel MOS transistors
84
and
85
, and N channel MOS transistors
86
and
87
. P channel MOS transistors
84
and
85
are connected between lines of power supply potential Vdd (3.3V) and an output node N
86
respectively. N channel MOS transistors
86
and
87
are serially connected between output node N
86
and a line of ground potential Vss. The gates of MOS transistors
84
and
87
receive an input signal VI (external signal EXTm), and the gates of MOS transistors
85
and
86
receive an activation signal SEL. Activation signal SEL is set to “L” level of a non-activation level in the standby mode (power down mode, sleep mode) of the semiconductor integrated circuit device in order to reduce consumption power. The potential at output node N
86
is an output signal VO.
When activation signal SEL is at “L” level of the non-activation level, P channel MOS transistor
85
is rendered conductive, N channel MOS transistor
86
is rendered nonconductive, and output signal VO is fixed at “H” level irrespective of input signal VI. When activation signal SEL rises to “H” level of an activation level, P channel MOS transistor
85
is rendered nonconductive, N channel MOS transistor
86
is rendered conductive and input buffer
81
.
m
is activated.
When input signal VI rises to “H” level (2V), P channel MOS transistor
84
is rendered nonconductive, N channel MOS transistor
87
is rendered conductive and output signal VO falls to “L” level. When input signal VI falls to “L” level (0.8V), P channel MOS transistor
84
becomes conductive, N channel MOS transistor
87
becomes nonconductive, and output signal VO rises to “H” level.
FIG. 12
is a partially omitted circuit block diagram showing an SSTL
—
3 (Stub Series Terminated Logic for 3.3V) which is a high speed interface.
Referring to
FIG. 12
, in the SSTL
—
3 interface, an output node
91
a
of an output buffer
91
in a semiconductor integrated circuit device
90
of transmission side is connected with one input node
93
a
of an input buffer
93
in a semiconductor integrated circuit device
92
of reception side by a signal transmission line
94
. Output node
91
a
of output buffer
91
and one input node
93
a
of input buffer
93
respectively receive terminal potential Vtt (1.65V) via resistance elements
95
and
96
. The other input node
93
b
of input buffer
93
receives reference potential VR (1.65V).
As shown in
FIG. 13
, input buffer
93
is constituted by a differential amplifier, and includes P channel MOS transistors
100
-
102
and N channel MOS transistors
103
and
104
. P channel MOS transistor
100
is connected between a line of power supply potential Vdd and a node N
100
, and its gate receives an activation signal/SEL. MOS transistors
101
and
103
as well as MOS transistors
102
and
104
are serially connected between node N
100
and a line of ground potential Vss. Both gates of P channel MOS transistors
101
and
102
are connected to the drain (node N
101
) of P channel MOS transistor
101
. P channel MOS transistors
101
and
102
constitute a current mirror circuit. The gates of N channel MOS transistors
103
and
104
respectively receive reference potential VR and input signal VI. N channel MOS transistors
103
and
104
constitute a pair of differential transistors. As shown in
FIG. 14
, input signal VI is a signal formed of a low amplitude logic signal overlapping reference potential VR, and oscillates between 1.65+0.4V and 1.65−0.4V. The potential at node N
102
between P channel MOS transistor
102
and N channel MOS transistor
104
is output signal VO.
When activation signal/SEL is at “H” level of the nonactivation level, P channel MOS transistor
100
becomes nonconductive, and output signal VO is fixed at “L” level irrespective of input signal VI. When activation signal/SEL falls to “L” level of the activation level, P channel MOS transistor
100
becomes conductive, current is supplied to nodes N
101
and N
102
respectively, and input buffer
93
is activated.
When input signal VI rises to “H” level (2.05V), the resistance value of N channel MOS transistor
104
becomes lower than that of N channel MOS transistor
103
, and output signal VO falls to “L” level. When input signal VI falls to “L” level (1.25V), the resistance value of N channel MOS transistor
104
becomes higher than that of N channel MOS transistor
103
, and the level of output signal VO becomes “H”.
In the SSTL
—
3 interface, the smaller amplitude of the potential of signal transmission line
94
enables high speed transmission of the signal. In addition, the alternating current component of the consumption power can be reduced. The reduced consumption power of output buffer
91
allows output buffer
91
to be easily integrated.
A problem which arises in this case is as follows. In the SSTL
—
3 interface, the potential of signal transmission line
94
needs to be maintained at terminal potential Vtt, and consumption power for generating terminal potential Vtt from power supply potential Vdd (=Vdd/2) is required, resulting in increased consumption power in the entire system. This problem is especially critical in the system such as a portable device which is driven by a battery.
According to a proposed method, terminal potential Vtt is set at power supply potential Vdd (3.3V), reference potential VR is set at 2.9V, and input signal VI is oscillated between 2.9+0.4V and 2.9−0.4V as shown in FIG.
15
. This method does not require the consumption power for generating terminal potential Vtt, so that the consumption power in the entire system is reduced. However, this method is not applicable to high speed operation since terminal potential Vtt is not equal to reference potential VR, and variation of signal VI from “H” level to “L” level and that from “L” level to “H” level are not balanced.
Then another method is proposed. According to this method, when the system is driven by a battery, terminal potential Vtt is s

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