Input buffer for integrated injection logic circuits

Details Input buffer for integrated injection logic circuits Input buffer for integrated injection logic circuits

1977-07-18

1979-12-25

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307203, 307DIG1, 357 15, H03K 1908

Patent

active

041807499

ABSTRACT:
An input buffer gate for integrated injection logic (I.sup.2 L) circuits, including a multiple-collector transistor wherein a first collector is electrically common with the base thereof, a second (Schottky) collector is connected to receive an input signal, and a third collector which drives internal I.sup.2 L gates. The buffer has a high input breakdown voltage, virtually no input capacitance, power-up/power-down capability at logic "1" and virtually no input current at logic "0", very low storage time, and an input "1" threshold of about 0.5 volts.

REFERENCES:
patent: 3790817 (1974-02-01), Dobkin
patent: 4013898 (1977-03-01), Makino
patent: 4081822 (1978-03-01), Dao et al.

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