Input buffer for CMOS integrated circuits

Details Input buffer for CMOS integrated circuits Input buffer for CMOS integrated circuits

2006-06-27

2009-02-24

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S333000, C326S062000

Reexamination Certificate

active

07495483

ABSTRACT:
An input buffer for CMOS integrated circuits using sub-micron CMOS technology is affected by the presence of high voltage between various ports of a device. An improvement for such a buffer provides an input voltage limiting circuit making the device mode tolerant to high voltages while using low voltage tolerant CMOS devices. This improvement also reduces the switching level uncertainty due to manufacturing process variations by adding compensation devices to a first inverter stage in the input buffering stage so as to increase noise margin. A hysteresis characteristic is produced by the circuit thus reducing the effect of manufacturing process variation. The circuit can be easily interfaced to other blocks and safely operates in conjunction with relatively high voltage CMOS technology circuitry while achieving the high-speed advantage of thin gate oxide. Low power consumption is achieved by avoiding the possibility of DC current flow in the circuitry.

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patent: 6784717 (2004-08-01), Hunt et al.
patent: 2005/0286333 (2005-12-01), Gupta et al.

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