Input buffer for analog-to-digital convertor

Details Input buffer for analog-to-digital convertor Input buffer for analog-to-digital convertor

2001-07-30

2003-03-25

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S067000, C327S073000, C327S087000, C327S089000, C330S254000, C330S278000

Reexamination Certificate

active

06538477

ABSTRACT:

FIELD OF INVENTION
The present invention relates to an input buffer for use in analog-to-digital converters. More particularly, the present invention relates to an input buffer circuit having high linearity, good noise performance and voltage swing capability and configured for increasing the input impedance of an analog-to-digital converter.
BACKGROUND OF THE INVENTION
The demand for more reliable integrated circuit components for use in communication, instrumentation and high-quality video applications continues to increase. As a result, integrated circuit manufacturers are requiring for such components and devices to meet the design requirements of a myriad of emerging applications. In particular, integrated circuit manufacturers are requiring analog-to-digital converters and related components to continue to improve data rates, noise reduction, and accuracy.
An increasingly popular technique used in improving the characteristics of analog to-digital converters includes the use of delta-sigma modulation wherein an analog voltage is input to a delta-sigma modulator, and the output can be digitally filtered to remove the noise. In analog-to-digital converters, such as delta-sigma A/D converters, the analog input signal must usually be sampled. To facilitate the sampling of the analog signal, A/D converters typically implement one of various switched-capacitor techniques.
With reference to
FIG. 1
, an example of switch-sampling circuit
100
having a sampling capacitor C
S
, with switches S
1
and S
2
being configured for receiving and sampling an input voltage V
IN
, is illustrated. During a phase one, switches S
1
are closed and capacitor C
S
is charged up to a voltage. During a phase two, switches S
1
are opened, switches S
2
are closed, and the charge in capacitor C
S
is provided to a summing node of the first integrator in the delta-sigma analog-to-digital converter. The analog-to-digital converter can then compare the voltage charge to an input reference voltage V
REF
to facilitate the determination of the digital representation of the input voltage V
IN
.
In such a switched-sampling circuit
100
, the input voltage V
IN
must be configured for providing the charge supplied to the sampling capacitor C
S
. The more frequently sampling circuit
100
is switched, the more charge that must be supplied to the sampling capacitor C
S
, thus increasing the demands on the input voltage V
IN
for driving the sampling capacitor C
S
. To lessen the load on the input voltage V
IN
, many analog-to-digital converters include a buffer amplifier
102
for isolating the input voltage V
IN
from sampling circuit
100
.
It is highly desirable that the buffer amplifier
102
maintain good linearity and noise performance, i.e., no degradation of the linearity or noise performance, as well as be able to swing close to ground during operation. Various configurations exist for providing input buffer amplifiers, but each of these configurations have one or more shortcomings.
For example, to obtain high linearity at low frequency, a high gain amplifier is needed within buffer amplifier
102
. One approach for providing this high gain characteristic can be achieved by cascading multiple gain stages to provide a high gain amplifier. However, such a cascading configuration requires frequency compensation to maintain stable feedback conditions. Further, such a cascading configuration produces undesirable wideband noise from the buffer amplifier
102
to switched-sampling circuit
100
. Another approach includes the implementation of cascode circuits in a single stage amplifier. Such a cascode configuration is generally limited when using a low power supply, wherein the voltage drop caused by stacking the cascode devices severely reduces the input signal range.
Another configuration for buffer amplifier
102
, disclosed in U.S. Pat. No. 5,644,257 to Kerth et al. (“Kerth”), provides a circuit configured for reducing the effects of a non-linear anti-aliasing network. The Kerth configuration utilizes a primary and secondary input path, wherein the secondary input path is turned on initially to provide the charging for the parasitic capacitance and to replenish the channeling charge lost in a previous sampling cycle, i.e., a “course” tuning of buffer amplifier
102
. Meanwhile, the primary input path is configured to provide the charge required by the sampling capacitor C
S
, i.e., to “fine” tune the voltage levels within switched-sampling circuit
100
during sampling operation. However, the Kerth configuration does not reduce or eliminate the loading on the input voltage terminal V
IN
.
Accordingly, a need exists for an input buffer circuit configured for increasing the input impedance of an analog-to-digital converter, and thus reducing the load on the input buffer circuit. In addition, a need exists for an improved input buffer configuration that provides high linearity and good noise performance, and can be configured to swing close to ground during operation.
SUMMARY OF THE INVENTION
The input buffer circuit according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, an input buffer circuit is configured to increase the input impedance of a switched-capacitor circuit, for example a switched-capacitor circuit of an analog-to-digital converter, and thus reduce the loading of the input voltage terminal V
IN
. In accordance with one aspect of the present invention, an input buffer circuit comprises a first amplifier configured with a second single stage amplifier to improve the overall gain of the input buffer circuit. In accordance with an exemplary embodiment, the first amplifier comprises a differential pair of transistors configured with a second pair of transistors comprising a current mirror arrangement, wherein one of the differential pair of transistors of the first amplifier is configured in a diode-connected arrangement to provide a first feedback loop, while the second amplifier comprises a differential pair of transistors configured with another pair of transistors also comprising a current mirror arrangement, with the second amplifier and the current mirror arrangement of the first amplifier comprising a second feedback loop.
In accordance with another aspect of the present invention, the input buffer circuit can be configured to maintain high linearity within the analog-to-digital converter. In accordance with this aspect, the input buffer circuit is suitably configured such that the drain-source voltages of the differential pair of transistors of the first amplifier are maintained at a constant, equal magnitude of voltage. As a result, any change in voltage appearing at the input terminal of the first amplifier will appear as a corresponding linear change in voltage on the output terminal of the first amplifier.
In accordance with another aspect of the present invention, the input buffer circuit is configured to maintain the noise performance within the analog-to-digital converter. In accordance with this aspect, the input buffer circuit is configured with the second feedback loop operating within the first feedback loop such that the input buffer circuit functions as a single stage amplifier, and thus does not degrade the noise performance of the analog-to-digital converter.
In accordance with another aspect of the present invention, the input buffer circuit is configured to swing substantially close to ground during operation. In accordance with this aspect of the present invention, the first amplifier is configured such that the differential pair of transistors comprise different sized transistor devices. Since the gate-source voltage V
GS
is inversely proportional to the device size, the gate-source voltage V
GS
of one transistor of the differential pair is smaller than the gate-source voltage V
GS
of the other transistor, thus creating an offset voltage which permits the input voltage to swing close to ground, and which maintains the output voltage at a voltage level higher than the in

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