Input buffer for a semiconductor memory device

Details Input buffer for a semiconductor memory device Input buffer for a semiconductor memory device

1997-06-25

1999-11-02

Nelms, David

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

3652335, 365193, G11C 800

Patent

active

059783109

ABSTRACT:
An input buffer for a memory device which receives a row address strobe RAS and produces a RAS1 from which the noise signal is removed. The device has a buffer input for externally receiving the RAS, a data output enable (DOE) locking portion for delaying the DOE signal for a predetermined time, and then producing a control signal for controlling the production of the output signal RAS1, and has a buffer output portion for receiving the RAS of the buffer input portion as an input signal and the control signal from the DOE locking portion, and producing the noise-free RAS1 in accordance with the control signal.

REFERENCES:
patent: 5019724 (1991-05-01), McClure
patent: 5036227 (1991-07-01), Jo et al.
patent: 5600607 (1997-02-01), Furutani et al.
patent: 5608688 (1997-03-01), Park
Patent Abstracts of Japan 02139792 A, published May 29, 1990 Japanese Patent Application 01176089 Jul. 7, 1989 (Toshiba Corp.).

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