Input buffer circuit with deglitch method and apparatus

Details Input buffer circuit with deglitch method and apparatus Input buffer circuit with deglitch method and apparatus

1992-11-23

1994-08-23

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307542, 307546, H03K 3295

Patent

active

053410335

ABSTRACT:
An input buffer circuit incorporates variable hysteresis levels to protect against unintended changes of output state in response to glitches in the input signal. The circuit is used in connection with input signals that alternate between LO and HI input states with known minimum periods between alternations. The switching threshold hysteresis for reverting back to a prior output state is boosted during the period following an input signal transition, with the boosted hysteresis removed following a delay period that is no greater than the minimum period between successive input signal transitions. Numerous circuit designs may be used to implement the varying hysteresis levels.

REFERENCES:
patent: 4464587 (1984-08-01), Suzuki et al.
patent: 4563594 (1986-01-01), Koyama
patent: 5113098 (1992-05-01), Teymouri
patent: 5175445 (1992-12-01), Kinugasa et al.
Glasser et al., The Design and Analysis of VLSI Circuits, Addison-Wesley Publishing Co., 1985, pp. 281-282.
Hodges et al., Analysis and Design of Digital Integrated Circuits, McGraw-Hill Book, co., 1983, pp. 335-337.

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