Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2000-04-07
2001-09-04
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S143000, C327S278000
Reexamination Certificate
active
06285230
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input buffer circuit, and in particular to an input buffer circuit which can compensate for a data hold time and reduce an operational current.
2. Description of the Background Art
FIG. 1
is a circuit diagram illustrating a conventional input buffer circuit
5
. Referring to
FIG. 1
, the input buffer circuit
5
includes: a NOR gate NOR
1
NORing a data signal DIN inputted to a data input pad and a control signal WECS into which an enable signal WE and a chip selection signal CS are combined; and a delay unit
1
, having first to n-th inverters INV
1
~INVn delaying an output signal from the NOR gate NOR
1
.
The first inverter INV
1
of the delay unit
1
includes: first and second PMOS transistors PM
1
, PM
2
and first and second NMOS transistors NM
1
, NM
2
connected in series between an external power voltage VCC and a ground voltage VSS. The gates of PM
1
, PM
2
, NM
1
and NM
2
are commonly connected to form an input terminal receiving an output signal from the NOR gate NOR
1
, and drains of the second PMOS transistor PM
2
and the first NMOS transistor NM
1
are commonly connected to form an output terminal outputting an output signal.
Each inverter INV
2
~INVn−1 is identically constituted to the first inverter INV
1
, and thus each input terminal is connected to an output terminal of a preceding inverter, and each output terminal is connected to an input terminal of a succeeding inverter.
In addition, the n-th inverter INVn is identically constituted to the first inverter INV
1
. Thus, an output signal from a preceding inverter INVn−1 is inputted to its input terminal, and an input data DATAIN is outputted from its output terminal.
The operation of the thusly-constituted input buffer circuit will now be described with reference to
FIGS. 2A-2D
.
First, when the data signal DIN as shown in FIG.
2
A and the low-level control signal WECS as shown in
FIG. 2B
are inputted, if a low external power voltage VCCL is applied to the input buffer circuit at the inverters'respective VCC terminals, the data signal DIN is delayed by the delay unit
1
, and thus outputted as the input data DATAIN as shown in FIG.
2
C.
On the other hand, when the data signal DIN as shown in FIG.
2
A and the low-level control signal WECS as shown in
FIG. 2B
are inputted, if a high external power voltage VCCH is applied to the input buffer circuit at the inverters'respective VCC terminals, the data signal DIN is delayed by the delay unit
1
, and thus outputted as the input data DATAIN as shown in FIG.
2
D.
As illustrated in
FIG. 2D
, when the delay unit
1
is driven by the high external power voltage VCCH, not the low external power voltage VCCL, a driving current is increased as much as the external power voltage VCC rises. Thus each inverter INV
1
~INVn operates rapidly. Accordingly, a delay rate is lowered.
When the conventional input buffer circuit
5
is operated by the high external power voltage VCCH during a write operation, one must add more inverters in order to obtain a sufficiently long data hold time. However, when the low external power voltage VCCL is applied, the conventional input buffer circuit is delayed due to the additional inverters. Thus its operational speed becomes slower.
Also, when the delay unit
1
is operated by the high external power voltage VCCH, the driving current is increased.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an input buffer that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
In accordance with the purpose of the invention, as embodied and broadly described, one aspect the invention includes a delay unit to delay an input signal, the delay unit being powered by an external power voltage and having an associated variable delay which is varied according to a detection signal and the external power voltage, the detection signal indicating whether the external power voltage is high or low.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate one embodiment of the invention and together with the description serve to explain the principles of the invention.
REFERENCES:
patent: 5121014 (1992-06-01), Huang
patent: 5323360 (1994-06-01), Pelley, III
patent: 5497117 (1996-03-01), Nakajima et al.
patent: 5680370 (1997-10-01), Hashimoto et al.
patent: 5768257 (1998-06-01), Khacherian et al.
patent: 6034557 (2000-03-01), Schultz et al.
Hyundai Electronics Industries Co,. Ltd.
Tran Toan
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