Input buffer circuit of a MOS memory device

Details Input buffer circuit of a MOS memory device Input buffer circuit of a MOS memory device

1987-01-16

1989-02-14

Popek, Joseph A.

Static information storage and retrieval

Addressing

307279, G11C 800

Patent

active

048051535

ABSTRACT:
An input buffer circuit of a MOS memory device includes an input terminal for receiving an address signal, complementary output terminals, and an inverter circuit which propagates the address signal from the input terminal to the complementary output terminals, to provide the complementary output terminals with an address signal and an inverted address signal. A transition of the address signal is detected as it is propagated through the inverter circuit, and the potentials of the complementary output terminals are equalized before the transition is propagated to the complementary output terminals.

REFERENCES:
patent: 4099265 (1978-07-01), Abe
patent: 4355377 (1982-10-01), Sud et al.

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