Input buffer circuit having equal duty cycle

Details Input buffer circuit having equal duty cycle Input buffer circuit having equal duty cycle

2003-03-13

2004-11-16

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S359000, C330S253000

Reexamination Certificate

active

06819143

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to semiconductor circuits and specifically to input buffer circuits for driving high speed signals.
DESCRIPTION OF RELATED ART
FIG. 1
shows a typical input buffer circuit
100
for use in High Speed Transceiver Logic (HSTL) applications. Input buffer circuit
100
includes a differential pair formed by NMOS transistors
102
and
104
, a current source
106
, and a current mirror formed by PMOS transistors
108
and
110
. An input signal V
in
is provided to the gate of transistor
102
, and a reference voltage V
ref
is provided to the gate of transistor
104
. Current source
106
provides a constant bias current I
bias
for the differential pair
102
and
104
. In response to a voltage differential between V
in
and V
ref
, the differential pair
102
and
104
generates a single-ended output signal at node
112
. A well-known buffer
114
coupled to node
112
drives an output waveform V
out
in response to the voltage signal at node
112
.
The currents I
102
and I
104
in transistors
102
and
104
, respectively, change in response to the differential voltage between V
in
and V
ref
. The sum of currents I
102
and I
104
always equals I
bias
. In addition, the common mode voltage V
cm
between transistors
102
and
104
tracks the average of V
in
and V
ref
, i.e., V
cm
=(V
in
+V
ref
)/2−V
T
, where V
T
, is the threshold voltage for the differential pair. When transistors
102
and
104
are matched, currents I
102
and I
104
are both equal to I
bias
/2 when V
in
and V
ref
are equal. Capacitor
116
models the parasitic capacitance at the common mode voltage V
CM
node.
When V
in
transitions to logic high, i.e., when V
in
>V
ref
, transistor
104
turns off and transistor
102
conducts nearly all of I
bias
. If transistors
108
and
110
are matched, transistor
110
will mirror the current I
102
so that I
110
=I
102
. Because transistor
104
is non-conductive, the current I
110
charges node
112
toward V
DD
. In response thereto, buffer
114
transitions V
out
to logic high. Conversely, when V
in
transitions to logic low, i.e., when V
in
<V
ref
, transistor
102
turns off and transistor
104
conducts nearly all of I
bias
. Because transistor
102
is non-conductive, transistor
110
mirrors a negligible amount of current, i.e., I
110
≈0. As a result, the current I
104
discharges node
112
toward ground potential. In response thereto, buffer
114
transitions V
out
to logic low.
Referring also to the illustrative timing diagram of
FIG. 2
, the rise time of node
112
for low-to-high transitions of V
in
is much faster than the fall time of node
112
for high-to-low transitions of V
in
For example, when V
in
transitions to logic high at time t1, transistor
102
quickly turns on, and the resultant mirrored current I
110
quickly charges output node
112
toward V
DD
. In response thereto, buffer
114
quickly drives V
out
to logic high just after time t1. The logic high level of V
in
causes the common mode voltage V
cm
to increase, albeit more slowly than V
in
(because of the parasitic capacitance
116
), which in turn causes a decrease in the gate to source voltages V
gs
, of transistor
104
. Thus, when V
in
transitions to logic low at time t2, the V
gs
of transistor
104
increases slowly because V
cm
is slow to transition. Specifically, as V
in
transitions to logic low, transistor
104
does not turn on until V
cm
falls at least one threshold voltage below V
ref
. Because V
cm
does not fall as quickly as V
in
, there is a delay in transistor
104
turning on to discharge output node
112
toward ground potential, and thus buffer
114
does not drive V
out
to logic low until time t3.
The delay (t3−t2) in
FIG. 2
driving V
out
to logic low undesirably alters the duty cycle of the output waveform V
out
, which in turn may lead to downstream logic and/or timing errors. In addition, the delay in driving V
out
to logic low may undesirably limit the speed of circuit
100
. Note that if the NMOS differential pair
102
and
104
is replaced by a PMOS differential pair, the fall time of V
out
will be faster than the rise time V
out
, which also undesirably alters the duty cycle of the output waveform V
out
. For the circuit
100
of
FIG. 1
, the duty cycle error may be 10% or more. Therefore, there is a need for an input buffer circuit that is able to effect fast yet balanced output waveform transitions.


REFERENCES:
patent: 6373782 (2002-04-01), Ikeda

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