Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-03-20
2004-12-21
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S408000, C326S083000
Reexamination Certificate
active
06833739
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an input buffer circuit of a semiconductor integrated circuit device, and, more particularly, to an input buffer circuit which receives a small amplitude signal.
As shown in
FIG. 1
, a conventional input buffer circuit
51
of a semiconductor integrated circuit includes a differential amplifier circuit
52
and a driver circuit
53
.
The differential amplifier circuit
52
, which is of a current mirror type, has P channel MOS (PMOS) transistors Tp
1
and Tp
2
, N channel MOS (NMOS) transistors Tn
1
and Tn
2
and an NMOS transistor Tn
3
. The PMOS transistors Tp
1
and Tp
2
form a current mirror section, the NMOS transistors Tn
1
and Tn
2
form a differential amplifier section and the NMOS transistor Tn
3
forms a constant current section.
The sources of the NMOS transistors Tn
1
and Tn
2
are connected together and to a low-potential power supply VSS via the NMOS transistor Tn
3
. A bias voltage BIAS is applied to the gate of the NMOS transistor Tn
3
. The drain of the NMOS transistor Tn
1
is connected to a high-potential power supply VDD via the PMOS transistor Tp
1
. The drain of the NMOS transistor Tn
2
is connected to the high-potential power supply VDD via the PMOS transistor Tp
2
. The gates of the PMOS transistors Tp
1
and Tp
2
are connected together and to the drain of the NMOS transistor Tn
1
. The drain of the NMOS transistor Tn
2
is connected to the driver circuit
53
.
The driver circuit
53
includes an inverter circuit comprising CMOS transistors. The driver circuit
53
provides internal circuits (not shown) of the semiconductor integrated circuit with an output signal OUT corresponding to a signal Z output from the node between the PMOS transistor Tp
2
and the NMOS transistor Tn
2
.
An input signal IN is applied to the gate of the NMOS transistor Tn
1
, and a signal /IN which is a complementary signal of the input signal IN is applied to the gate of the NMOS transistor Tn
2
. The differential amplifier circuit
52
amplifies a potential difference between the input signals IN and /IN and supplies the signal Z to the driver circuit
53
. The amplified signal Z is supplied via the driver circuit
53
to the internal circuits of the semiconductor integrated circuit as an output signal OUT.
The input buffer circuit
51
generates the output signal OUT having a full amplitude in response to the input signals IN and /IN both having small amplitudes and high-frequency.
Integrated circuits are designed to be used in a variety of ways (different environmental conditions) in order to reduce the development cost. The operational speed of semiconductor integrated circuits is ever increasing. Accordingly, attempts are being made to increase the speed of signals transferred between integrated circuits mounted on a board. The interface which uses a full-amplitude signal employs an input buffer circuit including a differential amplifier circuit in order to permit transfer of a small-amplitude signal (high-frequency signal). When the input signals IN and /IN have small amplitudes, therefore, it is necessary to employ the input buffer circuit
51
having the differential amplifier circuit
52
. In other words, when the input signals IN and /IN have small amplitudes, it is not possible to employ an input buffer circuit that uses a CMOS transistor type inverter circuit.
However, even if a full-amplitude output signal OUT (i.e., the amplifying operation of the differential amplifier circuit
52
) is unnecessary, the differential amplifier circuit
52
always operates and a constant current flows through the differential amplifier circuit
52
. This unfortunately increases the power dissipation.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an input buffer circuit with reduced power dissipation.
One aspect of the present invention provides an input buffer circuit which includes a differential amplifier circuit for receiving first and second input signals and generating an amplified signal corresponding to a voltage difference between the first and second input signals. A transfer circuit receives the first input signal and outputs a transfer circuit output signal having the same logical level as the first input signal. A control circuit is connected to the differential amplifier circuit and the transfer circuit and selectively enables the differential amplifier circuit and the transfer circuit in accordance with a control signal.
Another aspect of the present invention provides an input buffer circuit which includes a differential amplifier circuit for receiving first and second input signals and generating an amplified signal corresponding to a voltage difference between the first and second input signals. A first tri-state inverter circuit is connected to the differential amplifier circuit and receives the amplified signal from the differential amplifier circuit. A second tri-state inverter circuit receives the first input signal. A control circuit is connected to the differential amplifier circuit and the first and second tri-state inverter circuits and selectively enables the differential amplifier circuit and the first and second tri-state inverter circuits in accordance with a control signal.
Yet another aspect of the present invention provides a method of testing a semiconductor device. The semiconductor device includes an output buffer connected between an internal logic circuit and a device pad, and an input buffer connected between the internal logic circuit and the device pad. The input buffer includes a differential amplifier circuit for selectively amplifying an input signal thereto and a transfer circuit. First, a terminal resistor is connected between the device pad and a high potential power supply. Then, the input signal is supplied to the input buffer from the output buffer. The differential amplifier circuit of the input buffer generates an amplified input signal and the transfer circuit of the input buffer generates a transfer signal having the same logic level as the input signal. A control signal is provided to the input buffer to enable the differential amplifier circuit and disable the transfer circuit.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 5166558 (1992-11-01), Ohsawa
patent: 5563835 (1996-10-01), Oldham
patent: 5621340 (1997-04-01), Lee et al.
patent: 5739700 (1998-04-01), Martin
patent: 5751186 (1998-05-01), Nakao
patent: 5789948 (1998-08-01), Kim et al.
patent: 5811992 (1998-09-01), D'Souza
patent: 5889419 (1999-03-01), Fischer et al.
patent: RE36179 (1999-04-01), Shimoda
patent: 5920208 (1999-07-01), Park
patent: 5929655 (1999-07-01), Roe et al.
patent: 5929668 (1999-07-01), Kim
patent: 5949252 (1999-09-01), Taguchi
patent: 5949452 (1999-09-01), Jones
patent: 5994922 (1999-11-01), Aoki et al.
patent: 6023175 (2000-02-01), Nunomiya et al.
patent: 6111437 (2000-08-01), Patel
patent: 6194933 (2001-02-01), Ishino et al.
patent: 2-073719 (1990-03-01), None
Arent & Fox PLLC
Nguyen Long
LandOfFree
Input buffer circuit for semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Input buffer circuit for semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input buffer circuit for semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3289515