Input buffer circuit

Details Input buffer circuit Input buffer circuit

1998-09-25

1999-12-14

Le, Vu A.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

3652235, 36518905, G11C 800

Patent

active

060026375

ABSTRACT:
An input buffer circuit of a semiconductor memory device in which data is accessed by driving a decoder based on first and second internal address signals, the input buffer circuit including a first circuit for summing an input address and a chip selection signal to generate a first address signal, first and second inverters for inverting the first address signal and generating the first internal address signal and a second address signal, a detector circuit receiving the first internal address signal and the second address signal and detecting a HIGH of the first internal address signal and a LOW of the second address signal, and a second circuit for summing an output of the detection means and the second address signal and generating the second internal address signal.

REFERENCES:
patent: 5691953 (1997-11-01), Yeh et al.
patent: 5706246 (1998-01-01), Choi et al.

Affiliated with

Also associated with

Rating

Input buffer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Input buffer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input buffer circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-869786