Input buffer circuit

Details Input buffer circuit Input buffer circuit

2002-09-03

2004-08-31

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S333000, C326S081000

Reexamination Certificate

active

06784700

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of electronic circuits and more particularly to an input buffer circuit.
BACKGROUND OF THE INVENTION
Semiconductor processing techniques are constantly improving and as they improve the required power supply voltages are reduced. The best semiconductor processing techniques today only require power supply voltages of around 1.8 volts. These processing techniques create transistors commonly referred to as thin oxide transistors. Thin oxide transistors are faster and can be used to produce denser circuits. Unfortunately, thin oxide circuits commonly have to interface with older technology circuits that have high voltage power supplies (e.g., 2.5V, 3.0V or 3.3V). These high voltage circuits contain transistors commonly referred to as thick oxide transistors. When it is necessary to convert a signal from a high voltage to a low voltage, a buffer circuit is required. Prior art solutions use a buffer circuit that has both thick oxide transistors (components) and thin oxide transistors (components). As a result, the processing of these circuits is relatively complex and expensive. Creating a buffer circuit with transistors that are all thin oxide transistors is difficult since the gate oxide voltage stress limit of the thin oxide transistors is lower than the high voltages being applied from an external source. Another problem is creating an input buffer circuit with thin oxide transistors that does not consume supply current.
Thus there exists a need for an input buffer system that overcomes these problems.
SUMMARY OF INVENTION
An input buffer circuit includes a pass gate circuit coupled to an input. A pseudo-differential amplifier is coupled to the pass gate circuit. A level shifter is coupled to the pseudo-differential amplifier. Note that a pseudo-differential amplifier as used herein means a circuit that responds like a classical differential amplifier when the input voltage is in a range near a reference voltage on the other input, but that acts like a logic gate inverter when the input voltage is at a logic high or a logic low level. The reason for using the pseudo-differential amplifier is so the circuit does not consume supply current when the input voltage is at a logic high or logic low level. A classical differential amplifier would consume current under those circumstances.
In one embodiment an inverter is coupled to an output of the level shifter. In another embodiment, the pass gate circuit is formed with transistors that are all the thin oxide type transistors. In another embodiment, the pass gate circuit has a bias input.
In one embodiment, the pseudo differential amplifier does not consume supply current when an input to the pass gate circuit is at a high logic level. In another embodiment, the pseudo differential amplifier has a capacitor between a gate of a p-channel transistor and a gate of an n-channel transistor. In another embodiment, the pseudo differential amplifier has an isolation transistor. In one embodiment, the input buffer circuit has a low threshold pass gate transistor. This may be a native transistor in one embodiment. A pseudo differential amplifier is coupled to the low threshold pass gate transistor. In another embodiment, the pseudo differential amplifier is formed with devices that are all thin oxide devices. In another embodiment, the pseudo differential amplifier has a first p-channel transistor and a second p-channel transistor. The first p-channel transistor has a source coupled to a low voltage supply and the second p-channel transistor has a source coupled to a low voltage supply. In another embodiment, the pseudo differential amplifier has a first n-channel transistor that has a drain coupled to a drain of the first p-channel transistor and a second n-channel transistor that has a drain coupled to a drain of the second p-channel transistor. In yet another embodiment, the pseudo differential amplifier has a third n-channel transistor that has a source coupled to a ground and a drain that is coupled to a source of the first n-channel transistor and to a source of the second n-channel transistor. In one embodiment, a gate of the first p-channel transistor and a gate of the first n-channel transistor and a gate of the third n-channel transistor are coupled to an output of the low threshold pass gate transistor.
In one embodiment, the pseudo differential amplifier does not consume supply current when the input buffer is in a standby mode.
In one embodiment, the input buffer circuit has an input clipping circuit. A pseudo differential amplifier is coupled to the input clipping circuit. An inverter is coupled to the pseudo differential amplifier. In one embodiment, the input buffer circuit includes a level shifter coupled between the pseudo differential amplifier and the inverter.
In one embodiment, the input clipping circuit only has thin oxide transistors. In another embodiment, the input clipping circuit has a p-channel pass gate transistor and an n-channel pass gate transistor. In another embodiment, the input clipping circuit has a p-bias input and an n-bias input.
In one embodiment, the pseudo differential amplifier has an isolation transistor.


REFERENCES:
patent: 5744982 (1998-04-01), Chu
patent: 6023174 (2000-02-01), Kirsch
patent: 6400189 (2002-06-01), McDaniel
patent: 6483349 (2002-11-01), Sakata et al.
patent: 6483386 (2002-11-01), Cress et al.
patent: 6552569 (2003-04-01), Wert
patent: 6611157 (2003-08-01), Usui

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