Input buffer circuit

Details Input buffer circuit Input buffer circuit

1985-01-18

1987-07-21

Miller, Stanley D.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307264, 307451, 307473, 307475, H03K 1730, H03K 17693

Patent

active

046820523

ABSTRACT:
An input buffer circuit comprised of MOS transistors includes an input terminal for receiving a tri-state input signal capable of taking any one of three potential levels, such as V.sub.pp, V.sub.cc and V.sub.ss. The input buffer circuit also includes a first detecting circuit having a first threshold level located between V.sub.pp and V.sub.cc and a second detecting circuit having a second threshold level located between V.sub.cc and V.sub.ss. Also provided is a third detecting circuit connected to the first and second detecting circuits to determine the level of the input signal applied to the input terminal.

REFERENCES:
patent: 4302690 (1981-11-01), Gollinger et al.
patent: 4350906 (1982-09-01), Gillberg
patent: 4475050 (1984-10-01), Noufer
patent: 4503340 (1985-03-01), Linder
patent: 4543498 (1985-09-01), Gorecki
patent: 4572977 (1986-02-01), Takemae et al.
patent: 4584491 (1986-04-01), Ulmer

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