Input buffer capable of achieving quick response

Details Input buffer capable of achieving quick response Input buffer capable of achieving quick response

2001-01-09

2002-04-16

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S390000

Reexamination Certificate

active

06373297

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an electronic circuit, and more particularly, to an input buffer for amplifying the voltage swing range of an in put signal.
2. Description of the Related Art
An input buffer is an interface circuit for converting an externally provided input signal into an internal signal suitable for operation in an internal circuitry. For example, if an external signal input to a memory device is a transistor-transistor logic (TTL) level signal, an interface circuit is required for converting the external signal into a complementary metal oxide semiconductor (CMOS) level signal. One such interface circuit is an input buffer.
FIG. 1
is a circuit diagram of a conventional input buffer. Referring to
FIG. 1
, the conventional input buffer is a differential-amplifier-type circuit, including first and second PMOS transistors P
12
and P
14
and first and second NMOS transistors N
12
and N
14
.
A buffer input signal IN is applied to a gate terminal of the first NMOS transistor N
12
and a reference voltage VREF is applied to a gate terminal of the second NMOS transistor N
14
. The buffer input signal IN is then compared with the reference voltage VREF. If the voltage level of the buffer input signal IN is higher than that of the reference voltage VREF, more current flows through the first NMOS transistor N
12
than through the second NMOS transistor N
14
. Thus, the voltage level of a buffer output signal OUT goes up to that of a power supply voltage (VDD). If the voltage level of the buffer input signal IN is lower than that of the reference voltage VREF, more current flows through the second NMOS transistor N
14
than through the first NMOS transistor N
12
. Thus, the voltage level of the buffer output signal OUT goes down to the ground voltage (GND).
However, in the conventional input buffer, the buffer input signal IN is compared with the reference voltage VREF to then generate the buffer output signal OUT. Thus, the buffer output signal OUT fully swings, centered on the reference voltage VREF. In other words, in the conventional input buffer, the center of the voltage of the buffer output signal OUT may also change depending on a variation of the reference voltage VREF. Thus, there is a need for an additional reference voltage generation circuit for providing a stabilized reference voltage VREF. Also, the conventional input buffer is of a differential amplifier type. Therefore, it is difficult to achieve a high amplification factor and a high-speed operation due to a limitation in the amplifying capability.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the invention to provide an input buffer operating at high speed and having a large amplification factor and a stabilized mid-level voltage swing.
In an embodiment of the invention, an input buffer amplifies a buffer input signal and generates a buffer output signal. Preferably, the input buffer includes first and second direct-current (DC) voltage controllers, and first and second drivers. The first and the second direct-current (DC) voltage controllers generate first and second alternate-current (AC) signals having AC voltage components of the buffer input signal reflected thereon, respectively. And the first driver provides the buffer output signal, the voltage of which is driven to a first level in response to a first AC signal. The second driver provides the buffer output signal, the voltage of which is driven to a second level in response to the first AC signal. According to the input buffer of the invention, it is possible to obtain a buffer output signal having an increased operation speed, an improved amplification factor and a stabilized mid-level voltage swing.


REFERENCES:
patent: 4816773 (1989-03-01), Pricer
patent: 5537067 (1996-07-01), Carvajal et al.
patent: 5973512 (1999-10-01), Baker
patent: 6154069 (2000-11-01), Ebihara

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