Amplifiers – Sum and difference amplifiers
Reexamination Certificate
2003-01-22
2004-12-21
Nguyen, Khanh Van (Department: 2817)
Amplifiers
Sum and difference amplifiers
C330S252000
Reexamination Certificate
active
06833756
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to receivers, and more specifically to an input buffer amplifier having a centroidal layout.
2. Background Art
Receivers often include components that are connected together to process and retrieve data from a received signal. For instance, a typical receiver may include a programmable gain amplifier, analog mixers, various filters, and an analog-to-digital converter (ADC), all of which are typically connected together in series. The mentioned components operate on the received signal so as retrieve data that is typically delivered to a processor.
Often times, buffer amplifiers are inserted between the series components of the receiver to insure that the output of one component can sufficiently drive the input of the following component. For instance, a buffer amplifier may be needed to drive the ADC because the sampling performed by the ADC can cause signal distortion. Furthermore, the buffer amplifiers also operate to isolate any impedance mismatches between the receiver components.
In differential receivers, there is a positive signal path and a negative signal path to process the positive and negative components of the received differential signal. It is desirable that the electrical components, including the input buffer amplifier, are matched for the two signal paths. If the electrical components are not matched, then an offset voltage can develop between the two signal paths. Any offset voltage reduces receiver sensitivity to low power signals, and reduces overall receiver performance.
The circuit layout of a differential circuit (including a differential buffer amplifier) can cause the generation of the offset voltage that reduces the electrical performance of the differential circuit. An offset voltage between two differential paths reduces the net available dynamic range in the system. Furthermore, common mode offsets produce distortion in the amplifier.
The differential circuit can produce the unwanted offset voltages if the layout is not symmetrical between the positive and negative paths. This occurs because an unsymmetrical layout produces mismatched components in the two differential paths that cause the unwanted offset voltages. Therefore, what is needed is an input buffer layout that is symmetrical so as not to produce DC offset voltages.
BRIEF SUMMARY OF THE INVENTION
The present invention is an input buffer amplifier that has a symmetrical centroidal layout. The input buffer amplifier includes two half differential amplifiers that have substantially identical layouts. Each half amplifier receives the input signal in-parallel, and the differential outputs of the differential half amplifiers are wire-ored together. The input buffer amplifier is symmetrical about both horizontal and vertical lines of symmetry. In other words, the two half amplifiers are mirror images of each other about a vertical line of symmetry. Furthermore, each half amplifier is also a mirror image of itself about a horizontal line of symmetry. The FET devices forming the half amplifiers are interlaced to create the horizontal line of symmetry.
The horizontal and vertical symmetry of the buffer amplifier improves device matching between differential signal paths. The mentioned symmetry also averages out the effect of any process gradients across the substrate of the input buffer amplifier. In other words, the devices in the half amplifiers that process the positive and negative components of the differential signal are more closely matched. This reduces differential offsets and common mode offsets that can occur when devices are not matched properly. The reduction in differential offset and common mode offset improves the linearity and dynamic range of input buffer amplifier. The improved differential matching also reduces signal distortion and susceptibility to power supply noise.
Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.
REFERENCES:
patent: 5796301 (1998-08-01), Tanabe et al.
patent: 5990737 (1999-11-01), Czarnul et al.
patent: 5999052 (1999-12-01), Tang
Copy of International Search Report for Appln. No. PCT/US03/01909, mailed Sep. 10, 2003, 5 pages.
Broadcom Corporation
Nguyen Khanh Van
Sterne Kessler Goldstein & Fox P.L.L.C.
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