Input buffer

Details Input buffer Input buffer

2000-06-28

2002-10-01

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

C327S089000

Reexamination Certificate

active

06459556

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an input buffer, installed in a semiconductor integrated circuit, for shaping a signal in a TTL level (transistor-transistor logic) externally supplied to an internal signal in a COMS level to be outputted.
A semiconductor storage device which is typical as a semiconductor integrated circuit is activated in accordance with signals such as an address, control signal, data, etc. which are supplied from a connected system, and makes the corresponding operation such as read/write. In this case, the signal supplied from the system generally has a signal level of TTL. Therefore, in order to operate a CMOS circuit within the semiconductor storage device on the basis of the TTL level signal, it is necessary to provide an input buffer for shaping the input signal in the TTL level into an internal signal in a CMOS level. Such an input buffer is coupled with an input terminal of the semiconductor storage device to shape the address, control signal, data, etc. supplied through the input terminal.
FIG. 3
is a circuit diagram for explaining the configuration of a conventional input buffer.
In
FIG. 3
, reference numeral
11
denotes a P-channel type MOS transistor and reference numeral
12
denotes an N-channel MOS transistor.
A power source voltage Vcc is applied to the source terminal of the P-channel type MOS transistor
11
and a grounding voltage Vss is applied to the source terminal of the N-channel type MOS transistor
12
.
The gate terminal of the P-channel type MOS transistor
11
and that of the N-channel type MOS transistor
12
are commonly connected to an input terminal IN
14
through a transfer gate
13
which is an N-channel type MOS transistor with the power source voltage Vcc applied to a gate terminal. The drain terminal of the P-channel type MOS transistor
11
and that of the N-channel type MOS transistor
12
are commonly connected to an output terminal OUT
15
.
Meanwhile, in order to assure a high input voltage in a device microstructure, it was necessary to provide a transfer gate
13
at the front stage of the input buffer thereby to reduce the voltage applied to the gate terminal.
The above inverter-type input buffer presents the following problem. The input buffer adopts the circuit configuration including a transfer gate
13
serving as a protection circuit at the front stage of the CMOS inverter to which the input terminal
14
is connected. Therefore, where the gate potential of the transfer gate
13
is set at the power source voltage Vcc and the input signal to the input terminal IN
14
is Vcc, the gate input of the CMOS inverter is Vcc−Vtn (Vtn: threshold voltage of the N-channel type MOS transistor constituting the transfer gate
13
) so that the P-channel type MOS transistor
11
turns on. Thus, a through current flows.
In order to prevent the above mentioned through current, a feedback transistor may be provided between the output terminal and the gate terminals of the P-MOS transistor
11
as shown in FIG.
3
B. However, in this case, the threshold of the N-MOS transistor
13
is difficult to set. Thus, design margin is restricted.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an input buffer provided with a protection circuit which can suppress flow of an unnecessary through current due to the protection circuit.
In order to attain the above object, in accordance with the present invention, there is provided a differential input buffer having a differential amplifier
3
comprising: a protection circuit
4
located between an input terminal
1
and the differential amplifier, the protection circuit serving to protect a MOS transistor
5
constituting the differential amplifier when a high voltage is applied to the input terminal. Preferably, the protection circuit is an N-channel type MOS transistor with a drain electrode connected to the input terminal, a source electrode connected to a gate terminal of an N-channel type MOS transistor
5
constituting the differential amplifier
3
and a gate terminal supplied with a power source voltage Vcc. Preferably, a higher internal boosted voltage Vpp than the power source voltage is applied to the gate terminal of the N-channel type MOS transistor constituting the protection circuit.
In accordance with the invention, when a high voltage is applied to an input terminal, it is possible to suppress occurrence of the unnecessary through current owing to the protection circuit for protecting the MOS transistor constituting the differential amplifier, which is located between the input terminal and the differential amplifier.
By applying a higher voltage than a power source voltage to the gate terminal of the N-channel type MOS transistor serving as the protection circuit, it is possible to suppress the reduction in the capability of the differential input buffer during the low voltage operation which is due to the reduction in the input signal by the threshold value of the N-channel type MOS transistor.


REFERENCES:
patent: 5942921 (1999-08-01), Talaga, Jr.
patent: 6049111 (2000-04-01), Higuchi et al.
patent: 6087891 (2000-07-01), Yoon et al.

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