Input buffer

Details Input buffer Input buffer

2000-06-22

2001-10-02

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S407000, C327S299000

Reexamination Certificate

active

06297679

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an input buffer, and in particular to an input buffer for buffering and outputting an inputted signal.
In general, a semiconductor integrated circuit such as a microprocessor, a dynamic random access memory (DRAM) and a synchronous random access memory (SRAM) is fabricated by providing various transistors and other manual devices to a silicon wafer.
Any semiconductor device is provided with input and output signals according to its operational object, and a power supply terminal for driving the semiconductor device is required.
The power supply terminal is connected to the power supply of the system, and normally consists of the power line VDD or VCC and the ground line VSS. The input and output signals exist in a group. The group of the input and output signals is called a bus.
A signal inputted through an external signal pin of the semiconductor device has limitations. For example, in order to be inputted through the pin, an address signal must reach to the pin within a predetermined time before the enabling of a reference signal (for example, a clock signal or control signal). The predetermined time is a setup time ts (refer to FIG.
1
). In addition, an effective signal needs to be maintained for a predetermined time after the enabling of the reference signal. The predetermined time is a hold time th (refer to FIG.
1
).
Referring to
FIG. 1
, when the input signal has a small load, the setup time ts has a good property in the case A. In this case, the input signal is operated before the effective clock, and thus a load is generated on the hold time th. On the other hand, in the case B, when the input signal is delayed for a predetermined time due to a great load, the input signal may be inputted almost simultaneously with or later than the reference clock.
As described above, the setup time ts and the hold time have contrary properties.
When the setup time ts has a superior property, the hold time th has an inferior property, and vise versa.
The application environment of the semiconductor products generally has various modifications. Especially, in processing the input signals, the setup time ts is important in some systems, and the hold time th is important in other systems.
FIG. 2
is a block diagram illustrating a structure of a general input buffer. A buffer
14
converts an input signal inputsig inputted through a pin, namely an LVTTL logic signal to a CMOS logic state, and transmits the converted signal into a delay unit
16
. Thereafter, the delay unit
16
adjusts the setup/hold time according to the reference signal (clock signal CLK inputted to an internal clock generating unit
12
), and transmits the signal to a switching unit
18
.
When a delay time is increased in the delay unit
16
, the property of the hold time th is improved. In the case that the delay time is decreased in the delay unit
16
, the property of the setup time ts is improved. In general, the delay time is adjusted so that one of the setup time ts and hold time th cannot have an excessively excellent property.
An output from the delay unit
16
and an internal clock int_clk are ANDed in the switching unit
18
. A resultant signal thereof decides timing of generating the effective signal of the input signal to be used in a chip.
The state where the input signal is inputted to the external pin is divided into the states where the input signal is converted from low to high and high to low according to the LVTTL logic signal.
At this time, the conversion time of the input signal (rise time and fall time) may be different. In this case, a time interval between the setup time ts and the hold time th is increased. In addition, the conditions of the operation, such as voltage and temperature may be varied. It more increases the time interval.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an input buffer which can improve the properties of a setup time and a hold time of an input signal.
In order to achieve the above-described object of the present invention, there is provided an input buffer including: a buffer for receiving a signal through an input pin; a plurality of delay units for delaying the signal inputted from the buffer by a different delay time; and a selecting unit for selectively outputting one of the output signals from the plurality of delay units according to an externally-inputted reference signal and the logic variation of the input signal from the buffer.
There is also provided an input buffer including: a first buffer for receiving an externally-inputted reference signal; a second buffer for receiving a signal through an input pin; a plurality of delay units for delaying the signal inputted from the second buffer by a different time; an input signal conversion detecting unit for detecting level conversion of the input signal according to the logic state of the input signal from the second buffer on the basis of the reference signal from the first buffer; a selecting unit for compensating for a setup time and a hold time of the input signal by selectively outputting one of the output signals from the plurality of delay units according to the signal from the input signal conversion detecting unit; and a switching unit for receiving a signal from the selecting unit, and outputting an effective signal of the input signal.


REFERENCES:
patent: 4110639 (1978-08-01), Redwine
patent: 5740410 (1998-04-01), Mc Dermott
patent: 5880998 (1999-03-01), Tanimura et al.
patent: 5986943 (1999-11-01), Isa
patent: 6028462 (2000-02-01), Kyles

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