Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
1999-05-26
2002-02-12
Huynh, Kim (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000
Reexamination Certificate
active
06347026
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of electrostatic discharge protection circuits for protecting voltage and signal terminals and particularly to input and power protection circuits implemented in a complementary metal oxide semiconductor process that uses salicides.
2. Description of the Related Art
An integrated circuit typically contains a numbers of electronic components that are highly susceptible to damage from either an electrostatic discharge, referred to as an ESD pulse, or an overvoltage condition. ESD pulses can subject an unprotected integrated circuit to voltages in excess of 1000 volts, in either a positive or a negative direction. ESD pulses or an overvoltage condition can occur on an integrated circuit's signal or power supply terminal and can cause catastrophic damage via either route. Some form of protection circuitry is usually provided in an integrated circuit to reduce the likelihood of damage due to either cause. Several industry standard characterization models have also been developed to test the ESD robustness of any such protection circuitry for an integrated circuit.
The industry standard characterization model most used to test the ESD robustness of the protection circuitry for an integrated circuit is the human-body model (hereinafter “HBM”) which simulates the discharge from a human finger into a voltage or signal terminal. In this model, a capacitor is charged up to a certain voltage, known as the HBM voltage, and then discharged through a resistor into a signal terminal of the device under test with another terminal, typically a voltage terminal, tied to ground. In typical reliability testing, all the signal terminals of an integrated circuit are tested with respect to all power and ground terminals with both polarities of a given HBM voltage. In addition, signal terminals may be tested against other signal terminals and voltage terminals may be tested against ground terminals. Current leakage measurements at specified reverse voltages are then performed on the same set of terminals. If the HBM voltage applied to every terminal under test in the DUT is 2 kilovolts and the resulting leakage current of all terminals of the device under test is below a certain level, then the integrated circuit is said to be resistant to 2 kilovolts HBM.
For integrated circuits implemented solely using a standard complementary metal oxide semiconductor (hereinafter “CMOS”) fabrication process, the current protection circuits struggle to provide adequate HBM protection. The current protection circuit is comprised of a single metal oxide semiconductor field effect transistor (hereinafter “MOSFET”) and, when implemented between a voltage terminal and a ground terminal, has a drain connected to the voltage terminal and both a gate and a source connected to the ground terminal. Referring to
FIG. 1A
, a top view of such a prior art MOSFET is shown. The MOSFET
2
is comprised of a plurality of gate fingers
4
, a plurality of drain regions
6
, and a plurality of source regions
8
. Each gate finger
4
and adjacent drain region
6
and adjacent source region
8
defines a mini MOSFET
10
and collectively all the mini MOSFETs make up the MOSFET
2
. Although all the MOSFETs and hence mini MOSFETs are fabricated at the same time using the same standard CMOS fabrication process, variations exist and each mini MOSFET
10
has slightly different electrical characteristics.
When a HBM event of greater than 2 kilovolts is applied to the voltage terminal of the current generation of protection circuit, the MOSFET
2
must be able to safely handle approximately 1.4 amps for 150 nanoseconds in order to provide adequate protection. Such a HBM event is shown in
FIG. 1B and
, when applied to the plurality of drain regions
6
, the voltage at the drain regions
6
increases until the lowest first snapback trigger current and voltage associated with one of the mini MOSFETs is reached. This event is shown as t
1
in
FIG. 1B and
, at this time, the mini MOSFET
10
with the lowest first snapback trigger voltage enters into avalanche breakdown and creates a path for current to flow from the voltage terminal, through the drain region
6
, through the source region
8
, and to the ground terminal. This reduces the voltage between the drain regions
6
and the source regions
8
to a level below that of the lowest first snapback trigger voltage which thereby keeps the remainder of the mini MOSFETs off. As time progresses, the current flow through and voltage between the one mini MOSFET defined above increases. Both the current flow through and the voltage between this one mini MOSFET increases until the second snapback trigger current and voltage associated with the mini MOSFET is reached. In
FIG. 1B
, this is shown as t
2
. The magnitude of the second snapback trigger current is usually significantly higher than the magnitude of the first snapback trigger current while the magnitude of the second snapback trigger voltage is usually significantly less than the magnitude of the first snapback trigger voltage. Hence, the remainder of the mini MOSFETs still remain off. When time t
2
is reached, localized hot spots begin forming in the region of high joule heating in the one mini MOSFET defined above. However, as shown in
FIG. 1B
, the current flow through this one mini MOSFET continues to increase which increases the temperature at these localized hot spots to a level potentially above the silicon melting point thereby potentially causing thermal damage to this one mini MOSFET and ultimately either a short circuit or open circuit in the entire MOSFET which renders the entire input protection device inoperative.
For a much more detailed and complete discussion of several of the industry standard characterization models, including the HBM, along with MOSFETs as protection circuits, please refer the paper by Stephen G. Beebe entitled “Characterization, Modeling and Design of ESD Protection Circuits,” March 1998, Technical Report No. ICL 98-083, Integrated Circuits Laboratory, Department of Electrical Engineering, Stanford University, Stanford, Calif. 94305,Pages 1-54, which is hereby incorporated by reference.
This problem is further exasperated for protection circuits which are solely implemented using a fully salicided CMOS fabrication process. Self aligned suicides or salicides, as the term is more commonly known, provide a number of advantageous characteristics including the reduction of the sheet resistance of the contact, the prevention of spiking between the metal interconnection and the source/drain junctions, and the formation of an SiO
2
insulating layer within the silicide layer. However, from the prospective of designing a protection circuit which can withstand HBM voltages greater than several kilovolts, the use of salicides provides a highly adverse effect. Simply stated, the second snapback trigger current associated with any MOSFET fabricated in any fully salicided CMOS fabrication process is significantly less than the magnitude of such a second snapback trigger current associated with the same MOSFET fabricated in a CMOS fabrication process without the use of salicides. This significant reduction in the second snapback trigger current significantly reduces the magnitude of the current which any mini MOSFET can safely dissipate without thermal damage. This, in turn, reduces the magnitude of the HBM voltage which any MOSFET input protection device can handle and hence degrades the performance of any MOSFET input protection device fabricated from a fully salicided CMOS fabrication process.
For a more detailed description of the effect that salicides have on ESD performance of protection circuits, please refer to the paper by Ajith Amerasekera et al., entitled “Substrate Triggering and Salicide Effects on ESD Performance and Protection Circuit Design in Deep Submicron CMOS Processes,” IEDM (1995), Pages 547-550, which is hereby incorporated by reference.
A need thus exists for a protection circuit for use in an int
Chen Jau-Wen
Sung Roberto
Huynh Kim
LSI Logic Corporation
Luedeka Neely & Graham
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